View PIC16HV785T-EML_1500460.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2008 microchip technology inc. ds41249e pic16f785/hv785 data sheet 20-pin flash-based, 8-bit cmos microcontroller with two-phase asynchronous feedback pwm dual high-speed comparators and dual operational amplifiers
ds41249e-page ii ? 2008 microchip technology inc. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, rfpic and smartshunt are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, linear active thermistor, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, pickit, picdem, picdem.net, pictail, pic 32 logo, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2008, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
? 2008 microchip technology inc. ds41249e-page 1 pic16f785/hv785 high-performance risc cpu: ? only 35 instructions to learn: - all single-cycle instructions except branches ? operating speed: - dc ? 20 mhz oscillator/clock input - dc ? 200 ns instruction cycle ? interrupt capability ? 8-level seep hardware stack ? direct, indirect and relative addressing modes special microcontroller features: ? precision internal oscillator: - factory calibrated to 1% - software selectable frequency range of 8 mhz to 32 khz - software tunable - two-speed start-up mode - crystal fail detect for critical applications - clock mode switching during operation for power savings ? power-saving sleep mode ? wide operating voltage range (2.0v-5.5v) ? industrial and extended temperature range ? power-on reset (por) ? power-up timer (pwrt) and oscillator start-up timer (ost) ? brown-out reset (bor) with software control option ? enhanced low-current watchdog timer (wdt) with on-chip oscillator (software selectable nominal 268 seconds with full prescaler) with software enable ? multiplexed master clear with pull-up/input pin ? programmable code protection ? high-endurance flash/eeprom cell: - 100,000 write flash endurance - 1,000,000 write eeprom endurance - flash/data eeprom retention: > 40 years low-power features: ? standby current: - 30 na @ 2.0v, typical ? operating current: -8.5 a @ 32 khz, 2.0v, typical -100 a @ 1 mhz, 2.0v, typical ? watchdog timer current: -1 a @ 2.0v, typical ? timer1 oscillator current: -2 a @ 32 khz, 2.0v, typical peripheral features: ? high-speed comparator module with: - two independent analog comparators - programmable on-chip voltage reference (cv ref ) module (% of v dd ) - 1.2v band gap voltage reference - comparator inputs and outputs externally accessible - < 40 ns propagation delay - 2 mv offset, typical ? operational amplifier module with 2 independent op amps: - 3 mhz gbwp, typical - all i/o pins externally accessible ? two-phase asynchronous feedback pwm module: - complementary output with programmable dead band delay - infinite resolution analog duty cycle - sync output/input for multi-phase pwm -f osc /2 maximum pwm frequency ? a/d converter: - 10-bit resolution and 14 channels (2 internal) ? 17 i/o pins and 1 input-only pin: - high-current source/sink for direct led drive - interrupt-on-pin change - individually programmable weak pull-ups ? timer0: 8-bit timer/counter with 8-bit programmable prescaler ? enhanced timer1: - 16-bit timer/counter with prescaler - external gate input mode - option to use osc1 and osc2 in lp mode as timer1 oscillator, if intosc mode selected ? timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler ? capture, compare, pwm module: - 16-bit capture, max resolution 12.5 ns - compare, max resolution 200 ns - 10-bit pwm with 1 output channel, max frequency 20 khz ? in-circuit serial programming tm (icsp tm ) via two pins ? shunt voltage regulator (pic16hv785 only): - 5 volt regulation - 4 ma to 50 ma shunt range 20-pin flash-based 8-bit cmos microcontroller
pic16f785/hv785 ds41249e-page 2 ? 2008 microchip technology inc. dual in line pin diagram table 1: dual in line pin summary device program memory data memory i/o 10-bit a/d (ch) op amps comparators ccp two- phase pwm timers 8/16-bit shunt reg. flash (words) sram (bytes) eeprom (bytes) pic16f785 2048 128 256 17+1 12+2 2 2 1 1 2/1 0 pic16hv785 2048 128 256 17+1 12+2 2 2 1 1 2/1 1 i/o pin analog comp. op amps pwm timers ccp interrupt pull-ups basic ra0 19 an0 c1in+ ? ? ? ? ioc y icspdat ra1 18 an1/v ref c12in0- ? ? ? ? ioc y icspclk ra2 17 an2 c1out ? ? t0cki ? int/ioc y ? ra3 (1) 4? ? ? ???ioc y mclr /v pp ra4 3 an3 ? ? ? t1g ? ioc y osc2/clkout ra5 2 ? ? ? ? t1cki ? ioc y osc1/clkin rb4 13 an10 ? op2- ? ? ? ? ? ? rb5 12 an11 ? op2+ ? ? ? ? ? ? rb6 (2) 11 ? ? ? ? ? ? ? ? ? rb7 10 ? ? ? sync ? ? ? ? ? rc0 16 an4 c2in+ ? ? ? ? ? ? ? rc1 15 an5 c12in1- ? ph1 ? ? ? ? ? rc2 14 an6 c12in2- op2 ? ? ? ? ? ? rc3 7 an7 c12in3- op1 ? ? ? ? ? ? rc4 6 ? c2out ? ph2 ? ? ? ? ? rc5 5 ? ? ? ? ? ccp1 ? ? ? rc6 8 an8 ? op1- ? ? ? ? ? ? rc7 9 an9 ? op1+ ? ? ? ? ? ? ? 1 ? ? ? ? ? ? ? ? v dd ?20 ? ? ? ? ? ? ? ? v ss note 1: input only. 2: open drain. 20-pin pdip, soic, ssop v dd ra5/t1cki/osc1/clkin ra4/an3/t1g/osc2/clkout ra3/mclr /v pp rc5/ccp1 rc4/c2out/ph2 rc3/an7/c12in3-/op1 rc6/an8/op1- rc7/an9/op1+ rb7/sync v ss ra0/an0/c1in+/icspdat ra1/an1/c12in0-/v ref /icspclk ra2/an2/t0cki/int/c1out rc0/an4/c2in+ rc1/an5/c12in1-/ph1 rc2/an6/c12in2-/op2 rb4/an10/op2- rb5/an11/op2+ rb6 pic16f785/hv785 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
? 2008 microchip technology inc. ds41249e-page 3 pic16f785/hv785 qfn (4x4x0.9) pin diagram table 2: qfn pin summary i/o pin analog comp. op amps pwm timers ccp interrupt pull-ups basic ra0 16 an0 c1in+ ? ? ? ? ioc y icspdat ra1 15 an1/v ref c12in0- ? ? ? ? ioc y icspclk ra2 14 an2 c1out ? ? t0cki ? int/ioc y ? ra3 (1) 1 ? ? ? ???ioc y mclr /v pp ra4 20 an3 ? ? ? t1g ? ioc y osc2/clkout ra5 19 ? ? ? ? t1cki ? ioc y osc1/clkin rb4 10 an10 ? op2- ? ? ? ? ? ? rb5 9 an11 ? op2+ ? ? ? ? ? ? rb6 (2) 8 ? ? ? ? ? ? ? ? ? rb7 7 ? ? ? sync ? ? ? ? ? rc0 13 an4 c2in+ ? ? ? ? ? ? ? rc1 12 an5 c12in1- ? ph1 ? ? ? ? ? rc2 11 an6 c12in2- op2 ? ? ? ? ? ? rc3 4 an7 c12in3- op1 ? ? ? ? ? ? rc4 3 ? c2out ? ph2 ? ? ? ? ? rc5 2 ? ? ? ? ? ccp1 ? ? ? rc6 5 an8 ? op1- ? ? ? ? ? ? rc7 6 an9 ? op1+ ? ? ? ? ? ? ? 18 ? ? ? ? ? ? ? ? v dd ?17 ? ? ? ? ? ? ? ? v ss note 1: input only. 2: open drain. 1 2 3 4 5 11 12 13 14 15 6 7 8 9 10 20 19 18 17 16 rc3/an7/c12in3-/op1 v dd ra5/t1cki/osc1/clkin ra4/an3/t1g/osc2/clkout ra3/mclr /v pp rc5/ccp1 rc4/c2out/ph2 rc6/an8/op1- rc7/an9/op1+ rb7/sync v ss ra0/an0/c1in+/icspdat ra1/an1/c12in0-/v ref /icspclk ra2/an2/t0cki/int/c1out rc0/an4/c2in+ rc1/an5/c12in1-/ph1 rc2/an6/c12in2-/op2 rb4/an10/op2- rb5/an11/op2+ rb6 20-pin qfn pic16f785/hv785
pic16f785/hv785 ds41249e-page 4 ? 2008 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ............................................................. 5 2.0 memory organization ......................................................................................................... .......................................................... 9 3.0 clock sources ............................................................................................................... ............................................................. 23 4.0 i/o ports ................................................................................................................... .................................................................. 35 5.0 timer0 module ............................................................................................................... ............................................................ 49 6.0 timer1 module with gate control............................................................................................. .................................................. 51 7.0 timer2 module ............................................................................................................... ............................................................ 55 8.0 capture/compare/pwm (ccp) module ............................................................................................ ......................................... 57 9.0 comparator module........................................................................................................... ......................................................... 63 10.0 voltage references ......................................................................................................... ........................................................... 70 11.0 operational amplifier (opa) module ......................................................................................... ................................................. 75 12.0 analog-to-digital converter (a/d) module ................................................................................... ............................................... 79 13.0 two-phase pwm .............................................................................................................. ......................................................... 91 14.0 data eeprom memory ......................................................................................................... .................................................. 103 15.0 special features of the cpu ................................................................................................ .................................................... 107 16.0 voltage regulator.......................................................................................................... ........................................................... 126 17.0 instruction set summary .................................................................................................... ...................................................... 127 18.0 development support........................................................................................................ ....................................................... 137 19.0 electrical specifications.................................................................................................. .......................................................... 141 20.0 dc and ac characteristics graphs and tables ................................................................................ ....................................... 163 21.0 packaging information...................................................................................................... ........................................................ 187 appendix a: data sheet revision history........................................................................................ .................................................. 193 appendix b: migrating from other pic ? devices....................................................................................................................... ......... 193 index .......................................................................................................................... ........................................................................ 195 the microchip web site ......................................................................................................... ............................................................ 201 customer change notification service ........................................................................................... ................................................... 201 customer support ............................................................................................................... ............................................................... 201 reader response ................................................................................................................ .............................................................. 202 product identification system.................................................................................................. ........................................................... 203 to our valued customers it is our intention to provide our valued customers with the be st documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regardi ng this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2008 microchip technology inc. ds41249e-page 5 pic16f785/hv785 1.0 device overview this document contains device specific information for the pic16f785/hv785. it is available in 20-pin pdip, soic, ssop and qfn packages. figure 1-1 shows a block diagram of the pic16f785/hv785 device. table 1-1 shows the pinout description. figure 1-1: pic16f785/hv785 block diagram flash program memory 13 data bus 8 14 program bus instruction reg program counter ram file registers direct addr 7 ram addr 9 addr mux indirect addr fsr reg status reg mux alu w reg osc1/clkin osc2/clkout porta 8 8 8 3 8-level stack 128 bytes 2k x 14 (13-bit) power-up timer oscillator start-up timer power-on reset watchdog timer mclr v ss brown-out reset 2 analog timer0 timer1 data eeprom 256 bytes eedata eeaddr comparators an0 an1 an2 an3 c1in- c1in+ c1out t0cki int t1cki configuration v ref t1g portb an4 an5 an6 an7 v dd 8 timer2 c2in- c2in+ c2out ccp ccp1 an3 an8 an9 an10 an11 rb4 rb5 rb6 rb7 portc rc0 rc1 rc2 rc3 rc4 rc5 rc6 rc7 ra0 ra1 ra2 ra3 ra4 ra5 analog-to-digital converter op1 op1+ op1- op2 op2+ op2- dual op amps ph1 ph2 sync two-phase pwm voltage reference instruction decode and control timing generation 8 mhz internal oscillator 32 khz internal oscillator
pic16f785/hv785 ds41249e-page 6 ? 2008 microchip technology inc. table 1-1: pic16f785/hv78 5 pinout description name function input type output type description ra0/an0/c1in+/icspdat ra0 ttl cmos porta i/o wi th prog. pull-up and interrupt-on-change an0 an ? a/d channel 0 input c1in+ an ? comparator 1 non-inverting input icspdat st cmos serial programming data i/o ra1/an1/c12in0-/v ref / icspclk ra1 ttl cmos porta i/o with prog. pull-up and interrupt-on-change an1 an ? a/d channel 1 input c12in0- an ? comparator 1 and 2 inverting input v ref an an external voltage reference for a/d, buffered reference output icspclk st ? serial programming clock ra2/an2/t0cki/int/c1out ra2 st cmos porta i/o with prog. pull-up and interrupt-on-change an2 an ? a/d channel 2 input t0cki st ? timer0 clock input int st ? external interrupt c1out ? cmos comparator 1 output ra3/mclr /vpp ra3 ttl ? porta input with prog. pull-up and interrupt-on- change mclr st ? master clear with internal pull-up v pp hv ? programming voltage ra4/an3/t1g/osc2/ clkout ra4 ttl cmos porta i/o with prog. pull-up and interrupt-on-change an3 an ? a/d channel 3 input t1g st ? timer1 gate osc2 ? xtal crystal/resonator clkout ? cmos f osc /4 output ra5/t1cki/osc1/clkin ra5 ttl cmos porta i/o with prog. pull-up and interrupt-on-change t1cki st ? timer1 clock osc1 xtal ? crystal/resonator clkin st ? external clock input/rc oscillator connection rb4/an10/op2- rb4 ttl cmos portb i/o an10 an ? a/d channel 10 input op2- ? an op amp 2 inverting input rb5/an11/op2+ rb5 ttl cmos portb i/o an11 an ? a/d channel 11 input op2+ ? an op amp 2 non-inverting input rb6 rb6 ttl od portb i/o. open drain output rb7/sync rb7 ttl cmos portb i/o sync st cmos master pwm sync output or slave pwm sync input rc0/an4/c2in+ rc0 ttl cmos portc i/o an4 an ? a/d channel 4 input c2in+ an ? comparator 2 non-inverting input legend: ttl = ttl input buffer, st = schmitt trigger input buffer, an = analog, od = open drain output, hv = high voltage
? 2008 microchip technology inc. ds41249e-page 7 pic16f785/hv785 rc1/an5/c12in1-/ph1 rc1 ttl cmos portc i/o an5 an ? a/d channel 5 input c12in1- an ? comparator 1 and 2 inverting input ph1 ? cmos pwm phase 1 output rc2/an6/c12in2-/op2 rc2 ttl cmos portc i/o an6 an ? a/d channel 6 input c12in2- an ? comparator 1 and 2 inverting input op2 ? an op amp 2 output rc3/an7/c12in3-/op1 rc3 ttl cmos portc i/o an7 an ? a/d channel 7 input c12in3- an ? comparator 1 and 2 inverting input op1 ? an op amp 1 output rc4/c2out/ph2 rc4 ttl cmos portc i/o c2out ? cmos comparator 2 output ph2 ? cmos pwm phase 2 output rc5/ccp1 rc5 ttl cmos portc i/o ccp1 st cmos capture input/compare output rc6/an8/op1- rc6 ttl cmos portc i/o an8 an ? a/d channel 8 input op1- an ? op amp 1 inverting input rc7/an9/op1+ rc7 cmos portc i/o an9 an ? a/d channel 9 input op1+ an ? op amp 1 non-inverting input v ss v ss power ? ground reference v dd v dd power ? positive supply table 1-1: pic16f785/hv785 pi nout description (continued) name function input type output type description legend: ttl = ttl input buffer, st = schmitt trigger input buffer, an = analog, od = open drain output, hv = high voltage
pic16f785/hv785 ds41249e-page 8 ? 2008 microchip technology inc. notes:
? 2008 microchip technology inc. ds41249e-page 9 pic16f785/hv785 2.0 memory organization 2.1 program memory organization the pic16f785/hv785 has a 13-bit program counter capable of addressing an 8k x 14 program memory space. only the first 2k x 14 (0000h-07ffh) for the pic16f785/hv785 is physically implemented. access- ing a location above these boundaries will cause a wrap around within the first 2k x 14 space. the reset vector is at 0000h and the interrupt vector is at 0004h (see figure 2-1). figure 2-1: program memory map and stack for the pic16f785/hv785 2.2 data memory organization the data memory (see figure 2-2) is partitioned into four banks, which contain the general purpose registers (gpr) and the special function registers (sfr). the special function registers are located in the first 32 locations of each bank. register locations 20h-7fh in bank 0 and a0h-bfh in bank 1 are general purpose registers, implemented as static ram. the last sixteen register locations in bank 1 (f0h-ffh), bank 2 (170h-17fh), and bank 3 (1f0h-1ffh) point to addresses 70h-7fh in bank 0. all other ram is unimplemented and returns ? 0 ? when read. seven address bits are required to access any location in a data memory bank. two additional bits are required to access the four banks. when data memory is accessed directly, the seven least significant address bits are contained within the opcode and the two most significant bits are contained in the status register. rp0 and rp1 bits of the status register are the two most significant data memory address bits and are also known as the bank select bits. table 2-1 lists how to access the four banks of registers. table 2-1: bank selection 2.2.1 general purpose register file the register file banks are organized as 128 x 8 in the pic16f785/hv785. each register is accessed, either directly, by seven address bits within the opcode, or indirectly, through the file select register (fsr). when the fsr is used to access data memory, the eight least significant data memory address bits are contained in the fsr and the ninth most significant address bit is contained in the irp bit in the status register. (see section 2.4 ?indirect addressing, indf and fsr registers? ). 2.2.2 special function registers the special function registers are registers used by the cpu and peripheral functions for controlling the desired operation of the device (see table 2-2). these registers are static ram. the special registers can be classified into two sets: core and peripheral. the special function registers associated with the ?core? are described in this section. those related to the operation of the peripheral features are described in the section of that peripheral feature. pc<12:0> 13 0000h 0004 0005 07ffh 0800h 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program memory call, return retfie, retlw stack level 2 rp1 rp0 bank 0 00 bank 1 01 bank 2 10 bank 3 11
pic16f785/hv785 ds41249e-page 10 ? 2008 microchip technology inc. figure 2-2: data memory map of the pic16f785/hv785 indirect addr. (1) 00h indirect addr. (1) 80h indirect addr. (1) 100h indirect addr. (1) 180h tmr0 01h option_reg 81h tmr0 101h option_reg 181h pcl 02h pcl 82h pcl 102h pcl 182h status 03h status 83h status 103h status 183h fsr 04h fsr 84h fsr 104h fsr 184h porta 05h trisa 85h porta 105h trisa 185h portb 06h trisb 86h portb 106h trisb 186h portc 07h trisc 87h portc 107h trisc 187h 08h 88h 108h 188h 09h 89h 109h 189h pclath 0ah pclath 8ah pclath 10ah pclath 18ah intcon 0bh intcon 8bh intcon 10bh intcon 18bh pir1 0ch pie1 8ch 10ch pie1 18ch 0dh 8dh 10dh 18dh tmr1l 0eh pcon 8eh 10eh 18eh tmr1h 0fh osccon 8fh 10fh 18fh t1con 10h osctune 90h pwmcon1 110h 190h tmr2 11h ansel0 91h pwmcon0 111h 191h t2con 12h pr2 92h pwmclk 112h 192h ccpr1l 13h ansel1 93h pwmph1 113h 193h ccpr1h 14h 94h pwmph2 114h 194h ccp1con 15h wpua 95h 115h 195h 16h ioca 96h 116h 196h 17h 97h 117h 197h wdtcon 18h refcon 98h 118h 198h 19h vrcon 99h cm1con0 119h 199h 1ah eedat 9ah cm2con0 11ah 19ah 1bh eeadr 9bh cm2con1 11bh 19bh 1ch eecon1 9ch opa1con 11ch 19ch 1dh eecon2 (1) 9dh opa2con 11dh 19dh adresh 1eh adresl 9eh 11eh 19eh adcon0 1fh adcon1 9fh 11fh 19fh general purpose register 96 bytes 20h general purpose register 32 bytes a0h bfh 120h 1a0h 6fh c0h efh 16fh 1efh 70h accesses bank 0 f0h accesses bank 0 170h accesses bank 0 1f0h 7fh ffh 17fh 1ffh bank 0bank 1bank 2bank 3 unimplemented data memory locations, read as ? 0 ?. note 1: not a physical register. file address file address file address file address
? 2008 microchip technology inc. ds41249e-page 11 pic16f785/hv785 table 2-2: pic16f785/hv785 special function registers summary bank 0 addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor page bank 0 00h indf addressing this location uses contents of fsr to address data memory (not a physical register) xxxx xxxx 22,114 01h tmr0 timer0 module?s register xxxx xxxx 49,114 02h pcl program counter?s (pc) least significant byte 0000 0000 21,114 03h status irp rp1 rp0 to pd zdcc 0001 1xxx 15,114 04h fsr indirect data memory address pointer xxxx xxxx 22,114 05h porta (1) ? ? ra5 ra4 ra3 ra2 ra1 ra0 --x0 x000 35,114 06h portb (1) rb7 rb6 rb5 rb4 ? ? ? ? xx00 ---- 42,114 07h portc (1) rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 00xx 0000 45,114 08h ? unimplemented ? ? 09h ? unimplemented ? ? 0ah pclath ? ? ? write buffer for upper 5 bits of program counter ---0 0000 21,114 0bh intcon gie peie t0ie inte raie t0if intf raif 0000 0000 17,114 0ch pir1 eeif adif ccp1if c2if c1if osfif tmr2if tmr1if 0000 0000 19,114 0dh ? unimplemented ? ? 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 xxxx xxxx 52,114 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 xxxx xxxx 52,114 10h t1con t1ginv tmr1ge t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 53,114 11h tmr2 timer2 module register 0000 0000 55,114 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 55,114 13h ccpr1l capture/compare/pwm register1 low byte xxxx xxxx 58,114 14h ccpr1h capture/compare/pwm register1 high byte xxxx xxxx 58,114 15h ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 58,114 16h ? unimplemented ? ? 17h ? unimplemented ? ? 18h wdtcon ? ? ? wdtps3 wdtps2 wdtps1 wdtps0 swdten ---0 1000 122,114 19h ? unimplemented ? ? 1ah ? unimplemented ? ? 1bh ? unimplemented ? ? 1ch ? unimplemented ? ? 1dh ? unimplemented ? ? 1eh adresh most significant 8 bits of the left justified a/d result or 2 bits of right justified result xxxx xxxx 81,114 1fh adcon0 adfm vcfg chs3 chs2 chs1 chs0 go/done adon 0000 0000 83,114 legend: ? = unimplemented locations read as ? 0 ?, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented note 1: port pins with analog functions controlled by the ansel0 and ansel1 registers will read ? 0 ? immediately after a reset even though the data latches are either undefined (por) or unchanged (other resets).
pic16f785/hv785 ds41249e-page 12 ? 2008 microchip technology inc. table 2-3: pic16f785/hv785 special function registers summary bank 1 addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor page bank 1 80h indf addressing this location uses contents of fsr to address data memory (not a physical register) xxxx xxxx 22,114 81h option_reg rapu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 17,114 82h pcl program counter?s (pc) least significant byte 0000 0000 21,114 83h status irp rp1 rp0 to pd zdcc 0001 1xxx 15,114 84h fsr indirect data memory address pointer xxxx xxxx 22,114 85h trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 35,114 86h trisb trisb7 trisb6 trisb5 trisb4 ? ? ? ? 1111 ---- 42,114 87h trisc trisc7 trisc6 trisc5 tr isc4 trisc3 trisc2 trisc1 trisc0 1111 1111 45,114 88h ? unimplemented ? ? 89h ? unimplemented ? ? 8ah pclath ? ? ? write buffer for upper 5 bits of program counter ---0 0000 21,114 8bh intcon gie peie t0ie inte raie t0if intf raif 0000 000x 17,114 8ch pie1 eeie adie ccp1ie c2ie c1ie osfie tmr2ie tmr1ie 0000 0000 18,114 8dh ? unimplemented ? ? 8eh pcon ? ? ? sboren ? ?por bor ---1 --qq 20,114 8fh osccon ? ircf2 ircf1 ircf0 osts (1) hts lts scs -110 q000 33,114 90h osctune ? ? ? tun4 tun3 tun2 tun1 tun0 ---0 0000 28,114 91h ansel0 ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 1111 1111 82,114 92h pr2 timer2 module period register 1111 1111 55,114 93h ansel1 ? ? ? ? ans11 ans10 ans9 ans8 ---- 1111 82,114 94h ? unimplemented ? ? 95h wpua ? ? wpua5 wpua4 wpua3 (2) wpua2 wpua1 wpua0 --11 1111 36,114 96h ioca ? ? ioca5 ioca4 ioca3 ioca2 ioca1 ioca0 --00 0000 37,114 97h ? unimplemented ? ? 98h refcon ? ? bgst vrbb vren vroe cvroe ? --00 000- 73,114 99h vrcon c1vren c2vren vrr ? vr3 vr2 vr1 vr0 000- 0000 72,114 9ah eedat eedat7 eedat6 eedat5 eedat4 eedat3 eedat2 eedat1 eedat0 0000 0000 103,114 9bh eeadr eeadr7 eeadr6 eeadr5 eeadr4 eeadr3 eeadr2 eeadr1 eeadr0 0000 0000 103,114 9ch eecon1 ? ? ? ? wrerr wren wr rd ---- x000 104,114 9dh eecon2 eeprom control register 2 (not a physical register) ---- ---- 104,114 9eh adresl least significant 2 bits of the left justified a/d result or 8 bits of the right justified result xxxx xxxx 81,114 9fh adcon1 ? adcs2 adcs1 adcs0 ? ? ? ? -000 ---- 84,114 legend: ? = unimplemented locations read as ? 0 ?, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented note 1: bit resets to ? 0 ? with two-speed start-up and lp, xt or hs selected as the oscillator mode or fail-safe mode is enabled, otherwise this bit resets to ? 1 ?. 2: ra3 pull-up is enabled when mclre is ? 1 ? in configuration word.
? 2008 microchip technology inc. ds41249e-page 13 pic16f785/hv785 table 2-4: pic16f785/hv785 special function registers summary bank 2 addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor page bank 2 100h indf addressing this location uses contents of fsr to address data memory (not a physical register) xxxx xxxx 22,114 101h tmr0 timer0 module?s register xxxx xxxx 49,114 102h pcl program counter?s (pc) least significant byte 0000 0000 21,114 103h status irp rp1 rp0 to pd zdcc 0001 1xxx 15,114 104h fsr indirect data memory address pointer xxxx xxxx 22,114 105h porta (1) ? ? ra5 ra4 ra3 ra2 ra1 ra0 --x0 x000 35,114 106h portb (1) rb7 rb6 rb5 rb4 ? ? ? ? xx00 ---- 42,114 107h portc (1) rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 00xx 0000 45,114 108h ? unimplemented ? ? 109h ? unimplemented ? ? 10ah pclath ? ? ? write buffer for upper 5 bits of program counter ---0 0000 21,114 10bh intcon gie peie t0ie inte raie t0if intf raif 0000 0000 17,114 10ch ? unimplemented ? ? 10dh ? unimplemented ? ? 10eh ? unimplemented ? ? 10fh ? unimplemented ? ? 110h pwmcon1 ? comod1 comod0 cmdly4 cmdly3 cmdly2 cmdly1 cmdly0 -000 0000 101,114 111h pwmcon0 prsen pasen blank2 blank1 sync1 sync0 ph2en ph1en 0000 0000 93,114 112h pwmclk pwmase pwmp1 pwmp0 per4 per3 per2 per1 per0 0000 0000 94,114 113h pwmph1 pol c2en c1en ph4 ph3 ph2 ph1 ph0 0000 0000 95,114 114h pwmph2 pol c2en c1en ph4 ph3 ph2 ph1 ph0 0000 0000 96,114 115h ? unimplemented ? ? 116h ? unimplemented ? ? 117h ? unimplemented ? ? 118h ? unimplemented ? ? 119h cm1con0 c1on c1out c1oe c1pol c1sp c1r c1ch1 c1ch0 0000 0000 65,114 11ah cm2con0 c2on c2out c2oe c2pol c2sp c2r c2ch1 c2ch0 0000 0000 67,114 11bh cm2con1 mc1out mc2out ? ? ? ? t1gss c2sync 00-- --10 68,114 11ch opa1con opaon ? ? ? ? ? ? ? 0--- ---- 76,114 11dh opa2con opaon ? ? ? ? ? ? ? 0--- ---- 76,114 11eh ? unimplemented ? ? 11fh ? unimplemented ? ? legend: ? = unimplemented locations read as ? 0 ?, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented note 1: port pins with analog functions controlled by the ansel0 and ansel1 registers will read ? 0 ? immediately after a reset even though the data latches are either undefined (por) or unchanged (other resets).
pic16f785/hv785 ds41249e-page 14 ? 2008 microchip technology inc. table 2-5: pic16f785/hv785 special function registers summary bank 3 addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor page bank 3 180h indf addressing this location uses contents of fsr to address data memory (not a physical register) xxxx xxxx 22,114 181h option_re g rapu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 17,114 182h pcl program counter?s (pc) least significant byte 0000 0000 21,114 183h status irp rp1 rp0 to pd zdcc 0001 1xxx 15,114 184h fsr indirect data memory address pointer xxxx xxxx 22,114 185h trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 36,114 186h trisb trisb7 trisb6 trisb5 trisb4 ? ? ? ? 1111 ---- 42,114 187h trisc trisc7 trisc6 trisc5 tri sc4 trisc3 trisc2 trisc1 trisc0 1111 1111 45,114 188h ? unimplemented ? ? 189h ? unimplemented ? ? 18ah pclath ? ? ? write buffer for upper 5 bits of program counter ---0 0000 21,114 18bh intcon gie peie t0ie inte raie t0if intf raif 0000 0000 17,114 18ch ? unimplemented ? ? 18dh ? unimplemented ? ? 18eh ? unimplemented ? ? 18fh ? unimplemented ? ? 190h ? unimplemented ? ? 191h ? unimplemented ? ? 192h ? unimplemented ? ? 193h ? unimplemented ? ? 194h ? unimplemented ? ? 195h ? unimplemented ? ? 196h ? unimplemented ? ? 197h ? unimplemented ? ? 198h ? unimplemented ? ? 199h ? unimplemented ? ? 19ah ? unimplemented ? ? 19bh ? unimplemented ? ? 19ch ? unimplemented ? ? 19dh ? unimplemented ? ? 19eh ? unimplemented ? ? 19fh ? unimplemented ? ? legend: ? = unimplemented locations read as ? 0 ?, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
? 2008 microchip technology inc. ds41249e-page 15 pic16f785/hv785 2.2.2.1 status register the status register contains arithmetic status of the alu, the reset status and the bank select bits for data memory (sram). the status register can be the destination for any instruction, like any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register, because these instructions do not affect any status bits. for other instructions not affecting any status bits, see section 17.0 ?instruction set summary? . note: the c and dc bits operate as a borrow and digit borrow out bit, respectively, in subtraction. see the sublw and subwf instructions for examples. register 2-1: status: status register r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd zdc (1) c (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 irp: register bank select bit (used for indirect addressing) 1 = bank 2,3 (100h-1ffh) 0 = bank 0,1 (00h-ffh) bit 6-5 rp<1:0>: register bank select bits (used for direct addressing) 11 = bank 3 (180h-1ffh) 10 = bank 2 (100h-17fh) 01 = bank 1 (80h-ffh) 00 = bank 0 (00h-7fh) bit 4 to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/borrow bit ( addwf , addlw,sublw,subwf instructions) (1) 1 = a carry-out from the 4th low-order bit of the result occurred 0 = no carry-out from the 4th low-order bit of the result bit 0 c: carry/borrow bit ( addwf , addlw, sublw, subwf instructions) (1) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: for borrow , the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high-order or low-order bit of the source register.
pic16f785/hv785 ds41249e-page 16 ? 2008 microchip technology inc. 2.2.2.2 option_reg register the option register is a readable and writable register, which contains various control bits to configure the tmr0/wdt prescaler, the external ra2/int interrupt, the tmr0 and the weak pull-ups on porta. note: to achieve a 1:1 prescaler assignment for tmr0, assign the prescaler to the wdt by setting psa bit to ? 1 ? in the option reg- ister. see section 5.4 ?prescaler? . register 2-2: option_reg: option register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rapu intedg t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 rapu : porta pull-up enable bit 1 = porta pull-ups are disabled 0 = porta pull-ups are enabled by individual port latch values in wpua register bit 6 intedg: interrupt edge select bit 1 = interrupt on rising edge of ra2/an2/t0cki/int/c1out pin 0 = interrupt on falling edge of ra2/an2/t0cki/int/c1out pin bit 5 t0cs: tmr0 clock source select bit 1 = transition on ra2/an2/t0cki/int/c1out pin 0 = internal instruction cycle clock (clkout) bit 4 t0se: tmr0 source edge select bit 1 = increment on high-to-low transition on ra2/an2/t0cki/int/c1out pin 0 = increment on low-to-high transition on ra2/an2/t0cki/int/c1out pin bit 3 psa: prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0 ps<2:0>: prescaler rate select bits note 1: a dedicated 16-bit wdt postscaler is available for the pic16f785/hv785. see section 15.5 ?watchdog timer (wdt)? for more information. 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate (1)
? 2008 microchip technology inc. ds41249e-page 17 pic16f785/hv785 2.2.2.3 intcon register the interrupt control register is a readable and writable register, which contains the various enable and flag bits for tmr0 register overflow, porta change and external ra2/int pin interrupts. register 2-3: intcon: interrupt control register note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie bit of the intcon register. user software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie peie t0ie inte raie (1) t0if (2) intf raif bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 gie: global interrupt enable bit 1 = enables all unmasked interrupts 0 = disables all interrupts bit 6 peie: peripheral interrupt enable bit 1 = enables all unmasked peripheral interrupts 0 = disables all peripheral interrupts bit 5 t0ie: tmr0 overflow interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4 inte: ra2/an2/t0cki/int/c1out external interrupt enable bit 1 = enables the ra2/an2/t0cki/int/c1out external interrupt 0 = disables the ra2/an2/t0cki/int/c1out external interrupt bit 3 raie: porta change interrupt enable bit (1) 1 = enables the porta change interrupt 0 = disables the porta change interrupt bit 2 t0if: tmr0 overflow interrupt flag bit (2) 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 intf: ra2/an2/t0cki/int/c1out external interrupt flag bit 1 = the ra2/an2/t0cki/int/c1out external interrupt occurred (must be cleared in software) 0 = the ra2/an2/t0cki/int/c1out external interrupt did not occur bit 0 raif: porta change interrupt flag bit 1 = when at least one of the porta <5:0> pins changed state (must be cleared in software) 0 = none of the porta <5:0> pins have changed state note 1: ioca register must also be enabled. 2: t0if bit is set when timer0 rolls over. timer0 is unchanged on reset and should be initialized before clear- ing t0if bit.
pic16f785/hv785 ds41249e-page 18 ? 2008 microchip technology inc. 2.2.2.4 pie1 register the peripheral interrupt enable register 1 contains the interrupt enable bits, as shown in register 2-4. register 2-4: pie1: peripheral interrupt enable register 1 note: bit peie of the intcon register must be set to enable any peripheral interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eeie adie ccp1ie c2ie c1ie osfie tmr2ie tmr1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 eeie: ee write complete interrupt enable bit 1 = enables the ee write complete interrupt 0 = disables the ee write complete interrupt bit 6 adie: a/d converter interrupt enable bit 1 = enables the a/d converter interrupt 0 = disables the a/d converter interrupt bit 5 ccp1ie: ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 4 c2ie: comparator 2 interrupt enable bit 1 = enables the comparator 2 interrupt 0 = disables the comparator 2 interrupt bit 3 c1ie: comparator 1 interrupt enable bit 1 = enables the comparator 1 interrupt 0 = disables the comparator 1 interrupt bit 2 osfie: oscillator fail interrupt enable bit 1 = enables the oscillator fail interrupt 0 = disables the oscillator fail interrupt bit 1 tmr2ie: timer2 to pr2 match interrupt enable bit 1 = enables the timer2 to pr2 match interrupt 0 = disables the timer2 to pr2 match interrupt bit 0 tmr1ie: timer1 overflow interrupt enable bit 1 = enables the timer1 overflow interrupt 0 = disables the timer1 overflow interrupt
? 2008 microchip technology inc. ds41249e-page 19 pic16f785/hv785 2.2.2.5 pir1 register the peripheral interrupt register 1 contains the interrupt flag bits. register 2-5: pir1: peripheral interrupt register 1 note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie, in the intcon register). user software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eeif adif ccp1if c2if c1if osfif tmr2if tmr1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 eeif: eeprom write operation interrupt flag bit 1 = the write operation completed (must be cleared in software) 0 = the write operation has not completed or has not been started bit 6 adif: a/d interrupt flag bit 1 = a/d conversion complete 0 = a/d conversion has not completed or has not been started bit 5 ccp1if: ccp1 interrupt flag bit capture mode : 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode : 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode : unused in this mode bit 4 c2if: comparator 2 interrupt flag bit 1 = comparator 2 output has changed (must be cleared in software) 0 = comparator 2 output has not changed bit 3 c1if: comparator 1 interrupt flag bit 1 = comparator 1 output has changed (must be cleared in software) 0 = comparator 1 output has not changed bit 2 osfif: oscillator fail interrupt flag bit 1 = system oscillator failed, clock input has changed to intosc (must be cleared in software) 0 = system clock operating bit 1 tmr2if: timer2 to pr2 match interrupt flag bit 1 = timer2 to pr2 match occurred (must be cleared in software) 0 = timer2 to pr2 match has not occurred bit 0 tmr1if: timer1 overflow interrupt flag bit 1 = timer1 register overflowed (must be cleared in software) 0 = timer1 has not overflowed
pic16f785/hv785 ds41249e-page 20 ? 2008 microchip technology inc. 2.2.2.6 pcon register the power control register contains flag bits to allow differentiation between a power-on reset (por ), a brown-out reset (bor ), a watchdog timer (wdt) reset (wdt) and an external mclr reset. register 2-6: pcon: power control register u-0 u-0 u-0 r/w-1 u-0 u-0 r/w-0 r/w-x ? ? ? sboren (1) ? ?por bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 unimplemented: read as ? 0 ? bit 4 sboren: software bor enable bit (1) 1 = bor enabled 0 = bor disabled bit 3-2 unimplemented: read as ? 0 ? bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) note 1: boren<1:0> = 01 in configuration word for this bit to control the bor .
? 2008 microchip technology inc. ds41249e-page 21 pic16f785/hv785 2.3 pcl and pclath the program counter (pc) specifies the address of the instruction to fetch for execution. the program counter is 13 bits wide. the low byte is called the pcl register. the pcl register is readable and writable. the high byte of the pc register is called the pch register. this register contains pc<12:8> bits which are not directly readable or writable. all updates to the pch register goes through the pclath register. on any reset, the pc is cleared. figure 2-3 shows the two situations for loading the pc. the upper example of figure 2-3 shows how the pc is loaded on a write to pcl in the pclath register pch. the lower exam- ple of figure 2-3 shows how the pc is loaded during a call or goto instruction in the pclath register pch). 2.3.1 modifying pcl executing any instruction with the pcl register as the destination simultaneously causes the program counter pc<12:8> bits (pch) to be replaced by the contents of the pclath register. this allows the entire contents of the program counter to be changed by writing the desired upper 5 bits to the pclath register. when the lower 8 bits are written to the pcl register, all 13 bits of the program counter will change to the values contained in the pclath register and those being written to the pcl register. a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). care should be exercised when jumping into a look-up table or program branch table (computed goto ) by modifying the pcl register. assuming that pclath is set to the table start address, if the table length is greater than 255 instructions or if the lower 8 bits of the memory address rolls over from 0xff to 0x00 in the middle of the table, then pclath must be incremented for each address rollover that occurs between the table beginning and the target location within the table. for more information refer to application note an556, ? implementing a table read ? (ds00556). 2.3.2 program memory paging the call and goto instructions provide 11 bits of address to allow branching within any 2k program memory page. when using a call or goto instruction, the most significant bits of the address are provided by pclath<4:3> (page select bits). when using a call or goto instruction, the user must ensure that the page select bits are programmed so that the desired destina- tion program memory page is addressed. when the call instruction (or interrupt) is executed, the entire 13-bit pc return address is pushed onto the stack. therefore, manipulation of the pclath<4:3> bits are not required for the return or retfie instructions (which pops the address from the stack). figure 2-3: loading of pc in different situations 2.3.3 stack the pic16f785/hv785 family has an 8-level deep x 13-bit wide hardware stack (see figure 2-1). the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed or an interrupt causes a branch. the stack is poped in the event of a return, retlw or retfie instruction execution. pclath is not affected by a push or pop operation. the stack operates as a circular buffer. this means that after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. the tenth push overwrites the second push (and so on). note 1: there are no status bits to indicate stack overflow or stack underflow conditions. 2: there are no instructions/mnemonics called push or pop. these are actions that occur from the execution of the call, return, retlw and retfie instructions or the vectoring to an interrupt address. pc 12 8 7 0 5 pclath<4:0> pclath instruction with alu result goto, call opcode <10:0> 8 pc 12 11 10 0 11 pclath<4:3> pch pcl 87 2 pclath pch pcl pcl as destination
pic16f785/hv785 ds41249e-page 22 ? 2008 microchip technology inc. 2.4 indirect addressing, indf and fsr registers the indf register is not a physical register. addressing the indf register will cause indirect addressing. indirect addressing is possible by using the indf register. any instruction using the indf register actually accesses data pointed to by the file select register (fsr). reading indf itself indirectly will produce 00h. writing to the indf register indirectly results in a no operation (although status bits may be affected). an effective 9-bit address is obtained by concatenating the 8-bit fsr and the irp bit in the status register, as shown in figure 2-4. a simple program to clear ram location 20h-2fh using indirect addressing is shown in example 2-1. example 2-1: indirect addressing figure 2-4: direct/indirect addressing pic16f785/hv785 movlw 0x20 ;initialize pointer movwf fsr ;to ram next clrf indf ;clear indf register incf fsr ;increment pointer btfss fsr,4 ;all done? goto next ;no clear next continue ;yes continue note: for memory map detail see figure 2-2. data memory indirect addressing direct addressing bank select location select rp1 rp0 6 0 from opcode irp file select register 7 0 bank select location select 00 01 10 11 180h 1ffh 00h 7fh bank 0 bank 1 bank 2 bank 3
? 2008 microchip technology inc. ds41249e-page 23 pic16f785/hv785 3.0 clock sources 3.1 overview the pic16f785/hv785 has a wide variety of clock sources and selection features to allow it to be used in a wide range of applications while maximizing perfor- mance and minimizing power consumption. figure 3-1 illustrates a block diagram of the pic16f785/hv785 clock sources. clock sources can be configured from external oscilla- tors, quartz crystal resonators, ceramic resonators and resistor-capacitor (rc) circuits. in addition, the sys- tem clock source can be configured from one of two internal oscillators, with a choice of speeds selectable via software. additional clock features include: ? selectable system clock source between external or internal via software. ? two-speed clock start-up mode, which mini- mizes latency between external oscillator start-up and code execution. ? fail-safe clock monitor (fscm) designed to detect a failure of the external clock source (lp, xt, hs, ec or rc modes) and switch to the internal oscillator. the pic16f785/hv785 can be configured in one of eight clock modes. 1. ec ? external clock with i/o on ra4. 2. lp ? 32.768 khz watch crystal or ceramic resonator oscillator mode. 3. xt ? medium gain crystal or ceramic resonator oscillator mode. 4. hs ? high gain crystal or ceramic resonator mode. 5. rc ? external resistor-capacitor (rc) with f osc /4 output on ra4 6. rcio ? external resistor-capacitor with i/o on ra4. 7. intosc ? internal oscillator with f osc /4 output on ra4 and i/o on ra5. 8. intoscio ? internal oscillator with i/o on ra4 and ra5. clock source modes are configured by the fosc<2:0> bits in the configuration word (see section 15.0 ?special features of the cpu? ). once the pic16f785/hv785 is programmed and the clock source mode configured, it cannot be changed in the software. figure 3-1: pic16f785/hv785 clock source block diagram (cpu and peripherals) osc1 osc2 sleep external oscillator lp, xt, hs, rc, rcio, ec system clock postscaler mux mux 8 mhz 4 mhz 2 mhz 1 mhz 500 khz 125 khz 250 khz ircf<2:0> 111 110 101 100 011 010 001 000 31 khz power-up timer (pwrt) fosc<2:0> (configuration word) scs (osccon<0>) internal oscillator (osccon<6:4>) watchdog timer (wdt) fail-safe clock monitor (fscm) hfintosc 8 mhz lfintosc 31 khz
pic16f785/hv785 ds41249e-page 24 ? 2008 microchip technology inc. 3.2 clock source modes clock source modes can be classified as external or internal. ? external clock modes rely on external circuitry for the clock source. examples are oscillator modules (ec mode), quartz crystal resonators or ceramic resonators (lp, xt, and hs modes) and resistor- capacitor (rc mode) circuits. ? internal clock sources are contained internally within the pic16f785/hv785. the pic16f785/ hv785 has two internal oscillators; the 8 mhz high-frequency internal oscillator (hfintosc) and 31 khz low-frequency internal oscillator (lfintosc). the system clock can be selected between external or internal clock sources via the system clock selection (scs) bit (see section 3.5 ?clock switching? ). 3.3 external clock modes 3.3.1 oscillator start-up timer (ost) when the pic16f785/hv785 is configured for any of the crystal oscillator modes (lp, xt or hs), the oscil- lator start-up timer (ost) is enabled, which extends the reset period to allow the oscillator additional time to stabilize. the ost counts 1024 clock periods pres- ent on the osc1 pin following a power-on reset (por), a wake from sleep, or when the power-up timer (pwrt) has expired (if the pwrt is enabled). during this time, the program counter does not incre- ment and program execution is suspended. the ost ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is pro- viding a stable system clock to the pic16f785/hv785. table 3-1 shows examples where the oscillator delay is invoked. in order to minimize latency between external oscillator start-up and code execution, the two-speed clock start-up mode can be selected (see section 3.6 ?two- speed clock start-up mode? ). table 3-1: oscillator delay examples 3.3.2 ec mode the external clock (ec) mode allows an externally generated logic level as the system clock source. when operating in this mode, an external clock source is connected to osc1 pin and the ra4 pin is available for general purpose i/o. figure 3-2 shows the pin connections for ec mode. the oscillator start-up timer (ost) is disabled when ec mode is selected. therefore, there is no delay in operation after a power-on reset (por) or wake-up from sleep. because the pic16f785/hv785 design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. upon restarting the external clock, the device will resume operation as if no time had elapsed. figure 3-2: external clock (ec) mode operation switch from switch to frequency oscillator delay comments sleep/por intrc intosc 31 khz 125 khz-8 mhz 5 s-10 s (approx.) cpu start-up (1) following a wake-up from sleep mode or por, cpu start-up is invoked to allow the cpu to become ready for code execution. sleep ec, rc dc ? 20 mhz lfintosc (31 khz) ec, rc dc ? 20 mhz sleep/por lp, xt, hs 31 khz-20 mhz 1024 clock cycles (ost) lfintosc (31 khz) intosc 125 khz-8 mhz 1 s (approx.) note 1: the 5 s-10 s start-up delay is based on a 1 mhz system clock. osc1/clkin i/o (osc2) ra4 clock from ext. system pic16f785/hv785
? 2008 microchip technology inc. ds41249e-page 25 pic16f785/hv785 3.3.3 lp, xt, hs modes the lp, xt and hs modes support the use of quartz crystal resonators or ceramic resonators connected to the osc1 and osc2 pins (figure 3-1). the mode selects a low, medium or high gain setting of the inter- nal inverter-amplifier to support various resonator types and speed. lp oscillator mode selects the lowest gain setting of the internal inverter-amplifier. lp mode current con- sumption is the least of the three modes. this mode is best suited to drive resonators with a low drive level specification, for example, tuning fork type crystals. xt oscillator mode selects the intermediate gain set- ting of the internal inverter-amplifier. xt mode current consumption is the medium of the three modes. this mode is best suited to drive resonators with a medium drive level specification, for example, at-cut quartz crystal resonators. hs oscillator mode selects the highest gain setting of the internal inverter-amplifier. hs mode current con- sumption is the highest of the three modes. this mode is best suited for resonators that require a high drive setting, for example, at-cut quartz crystal resonators or ceramic resonators. figure 3-3 and figure 3-4 show typical circuits for quartz crystal and ceramic resonators, respectively. figure 3-3: quartz crystal operation (lp, xt or hs mode) figure 3-4: ceramic resonator operation (xt or hs mode) table 3-2: ceramic resonators note 1: quartz crystal characteristics vary according to type, package and manufac- turer. the user should consult the manu- facturer data sheets for specifications and recommended application. 2: always verify oscillator performance over the v dd and temperature range that is expected for the application. note 1: a series resistor (r s ) may be required for quartz crystals with low drive level. 2: the value of r f varies with the oscillator mode selected (typically between 2 m to 10 m ) . c1 c2 quartz osc2 r s (1) osc1 r f (2) sleep to internal logic crystal pic16f785/hv785 mode freq. osc1 (c1) osc2 (c2) xt 455 khz 2.0 mhz 68-100 pf 15-68 pf 68-100 pf 15-68 pf hs 4.0 mhz 8.0 mhz 16.0 mhz 10-68 pf 15-68 pf 10-22 pf 10-68 pf 15-68 pf 10-22 pf note: these values are for design guidance only. see notes following this table. note 1: a series resistor (r s ) may be required for ceramic resonators with low drive level. 2: the value of r f varies with the oscillator mode selected (typically between 2 m to 10 m ) . 3: an additional parallel feedback resistor (r p ) may be required for proper ceramic resonator operation (typical value 1 m ). c1 c2 ceramic osc2 r s (1) osc1 r f (2) sleep to internal logic r p (3) resonator pic16f785/hv785
pic16f785/hv785 ds41249e-page 26 ? 2008 microchip technology inc. table 3-3: capacitor selection for crystal oscillator 3.3.4 external rc modes the external resistor-capacitor (rc) modes support the use of an external rc circuit. this allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. there are two modes, rc and rcio. in rc mode, the rc circuit connects to the osc1 pin. the osc2/clkout pin outputs the rc oscillator frequency divided by 4. this signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. figure 3-5 shows the rc mode connections. figure 3-5: rc mode in rcio mode, the rc circuit is connected to the osc1 pin. the osc2 pin becomes an additional general purpose i/o pin. the i/o pin becomes bit 4 of porta (ra4). figure 3-6 shows the rcio mode connections. figure 3-6: rcio mode the rc oscillator frequency is a function of the supply voltage, the resistor (r ext ) and capacitor (c ext ) values and the operating temperature. in addition to this, the oscillator frequency will vary from unit-to-unit due to normal threshold voltage. furthermore, the dif- ference in lead frame capacitance between package types will also affect the oscillation frequency or low c ext values. the user also needs to take into account variation due to tolerance of external rc components used. osc type crystal freq. cap. range c1 cap. range c2 lp 32 khz 15-33 pf 15-33 pf xt 200 khz 47-68 pf 47-68 pf 1 mhz 15-33 pf 15-33 pf 4 mhz 15-33 pf 15-33 pf hs 4 mhz 15-33 pf 15-33 pf 8 mhz 15-33 pf 15-33 pf 20 mhz 15-33 pf 15-33 pf note: these values are for design guidance only. see notes following this table. note 1: higher capacitance increases the stability of the oscillator, but also increases the start-up time. 2: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 3: rs may be required to avoid overdriving crystals with low drive level specification. osc2/clkout c ext r ext osc1 f osc /4 internal clock v dd v ss recommended values: 3 k r ext 100 k (v dd 3.0v) 10 k r ext 100 k (v dd < 3.0v) c ext > 20 pf pic16f785/hv785 c ext r ext osc1 internal clock v dd v ss i/o (osc2) ra4 pic16f785/hv785 recommended values: 3 k r ext 100 k (v dd 3.0v) 10 k r ext 100 k (v dd < 3.0v) c ext > 20 pf
? 2008 microchip technology inc. ds41249e-page 27 pic16f785/hv785 3.4 internal clock modes the pic16f785/hv785 has two independent, internal oscillators that can be configured or selected as the system clock source. 1. the hfintosc (high-frequency internal oscil- lator) is factory calibrated and operates at 8 mhz. the frequency of the hfintosc can be user adjusted 12% via software using the osctune register (register 3-1). 2. the lfintosc (low-frequency internal oscillator) is uncalibrated and operates at approximately 31 khz. the system clock speed can be selected via software using the internal oscillator frequency select (ircf) bits. the system clock can be selected between external or internal clock sources via the system clock selection (scs) bit (see section 3.5 ?clock switching? ). 3.4.1 intrc and intrcio modes the intrc and intrcio modes configure the internal oscillators as the system clock source when the device is programmed using the oscillator selection (fosc) bits in the configuration word (register 12-1). in intrc mode, the osc1 pin is available for general purpose i/o. the osc2/clkout pin outputs the selected internal oscillator frequency divided by 4. the clkout signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. in intrcio mode, the osc1 and osc2 pins are available for general purpose i/o. 3.4.2 hfintosc the high-frequency internal oscillator (hfintosc) is a factory calibrated 8 mhz internal clock source. the frequency of the hfintosc can be altered approximately 12% via software using the osctune register (register 3-1). the output of the hfintosc connects to a postscaler and multiplexer (see figure 3-1). one of seven frequencies can be selected via software using the ircf bits (see section 3.4.4 ?frequency select bits (ircf)? ). the hfintosc is enabled by selecting any frequency between 8 mhz and 125 khz (ircf 000 ) as the system clock source (scs = 1 ) or when two-speed start-up is enabled (ieso = 1 and ircf 000 ). the hf internal oscillator (hts) bit, in the osccon register, indicates whether the hfintosc is stable or not. 3.4.2.1 calibration bits the 8 mhz high-frequency internal oscillator (hfin- tosc) is factory calibrated. the hfintosc calibra- tion bits are stored in the calibration word (calib) located in program memory location 2008h. the cali- bration word is not erased using the specified bulk erase sequence in the ? pic16f785/hv785 memory programming specification ? (ds41237) and does not require reprogramming. reference the ? pic16f785/ hv785 memory programming specification ? (ds41237) for more information on the calibration word register. note: address 2008h is beyond the user program memory space. it belongs to the special configuration memory space (2000h- 3fffh), which can be accessed only during programming. see ? pic16f785/hv785 memory programming specification ? (ds41237) for more information.
pic16f785/hv785 ds41249e-page 28 ? 2008 microchip technology inc. 3.4.2.2 osctune register the hfintosc is factory calibrated but can be adjusted in software by writing to the osctune register (register 3-1). the osctune register has a nominal tuning range of 12%. the default value of the osctune register is ? 0 ?. the value is a 5-bit two?s complement number. due to process variation, the monotonicity and frequency step cannot be specified. when the osctune register is modified, the hfintosc frequency will begin shifting to the new frequency. the hfintosc clock will stabilize within 1 ms. code execution continues during this shift. there is no indication that the shift has occurred. osctune does not affect the lfintosc frequency. operation of features that depend on the lfintosc clock source frequency, such as the power-up timer (pwrt), watchdog timer (wdt), fail-safe clock monitor (fscm) and peripherals, are not affected by the change in frequency. register 3-1: osctune: oscillator t uning register u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? tun4 tun3 tun2 tun1 tun0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 unimplemented: read as ? 0 ? bit 4-0 tun<4:0>: frequency tuning bits 01111 = maximum frequency 01110 = ? ? ? 00001 = 00000 = center frequency. oscillator module is running at the calibrated frequency. 11111 = ? ? ? 10000 = minimum frequency
? 2008 microchip technology inc. ds41249e-page 29 pic16f785/hv785 3.4.3 lfintosc the low-frequency internal oscillator (lfintosc) is an uncalibrated (approximate) 31 khz internal clock source. the output of the lfintosc connects to a postscaler and multiplexer (see figure 3-1). 31 khz can be selected via software using the ircf bits (see section 3.4.4 ?frequency select bits (ircf)? ). the lfintosc is also the frequency for the power-up timer (pwrt), watchdog timer (wdt) and fail-safe clock monitor (fscm). the lfintosc is enabled by selecting 31 khz (ircf = 000 ) as the system clock source (scs = 1 ), or when any of the following are enabled: ? two-speed start-up (ieso = 1 and ircf = 000 ) ? power-up timer (pwrt) ? watchdog timer (wdt) ? fail-safe clock monitor (fscm) the lf internal oscillator (lts) bit, in the osccon register, indicates whether the lfintosc is stable or not. 3.4.4 frequency select bits (ircf) the output of the 8 mhz hfintosc and 31 khz lfin- tosc connect to a postscaler and multiplexer (see figure 3-1). the internal oscillator frequency select bits ircf<2:0> in the osccon register select the fre- quency output of the internal oscillators. one of eight frequencies can be selected via software: ?8 mhz ? 4 mhz (default after reset) ?2 mhz ?1 mhz ? 500 khz ? 250 khz ? 125 khz ?31 khz 3.4.5 hf and lf intosc clock switch timing when switching between the lfintosc and the hfin- tosc, the new oscillator may already be shut down to save power. if this is the case, there is a 10 s delay after the ircf bits are modified before the frequency selection takes place. the lts/hts bits will reflect the current active status of the lfintosc and the hfin- tosc oscillators. the timing of a frequency selection is as follows: 1. ircf bits are modified. 2. if the new clock is shut down, a 10 s clock start- up delay is started. 3. clock switch circuitry waits for a falling edge of the current clock. 4. clkout is held low and the clock switch circuitry waits for a rising edge in the new clock. 5. clkout is now connected with the new clock. hts/lts bits are updated as required. 6. clock switch is complete. if the internal oscillator speed selected is between 8 mhz and 125 khz, there is no start-up delay before the new frequency is selected. this is because the old and the new frequencies are derived from the hfintosc via the postscaler and multiplexer. note: following any reset, the ircf bits are set to ? 110 ? and the frequency selection is forced to 4 mhz. the user can modify the ircf bits to select a different frequency. note: care must be taken to ensure an invalid voltage or frequency selection is not selected. an example of an invalid config- uration is selecting 8 mhz when v dd is 2.0v.
pic16f785/hv785 ds41249e-page 30 ? 2008 microchip technology inc. 3.5 clock switching the system clock source can be switched between external and internal clock sources via software using the system clock select (scs) bit. 3.5.1 system clock select (scs) bit the system clock select (scs) bit, in the osccon register, selects the system clock source that is used for the cpu and peripherals. ? when scs = 0 , the system clock source is deter- mined by configuration of the fosc<2:0> bits in configuration word (config). ? when scs = 1 , the system clock source is cho- sen by the internal oscillator frequency selected by the ircf bits. after a reset, scs is always cleared. 3.5.2 oscillator start-up time-out status bit the oscillator start-up time-out status (osts) bit, (osccon<3>), indicates whether the system clock is running from the external clock source as defined by the fosc bits, or from internal clock source. in partic- ular, osts indicates that the oscillator start-up timer (ost) has timed out for lp, xt or hs modes. 3.6 two-speed clock start-up mode two-speed start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. in applications that make heavy use of the sleep mode, two-speed start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. this mode allows the application to wake-up from sleep, perform a few instructions using the intosc as the clock source and go back to sleep without waiting for the primary oscillator to become stable. when the pic16f785/hv785 is configured for lp, xt or hs modes, the oscillator start-up timer (ost) is enabled (see section 3.3.1 ?oscillator start-up timer (ost)? ). the ost timer will suspend program execution until 1024 oscillations are counted. two- speed start-up mode minimizes the delay in code exe- cution by operating from the internal oscillator as the ost is counting. when the ost count reaches 1024 and the osts bit in the osccon register is set, pro- gram execution switches to the external oscillator. 3.6.1 two-speed start-up mode configuration two-speed start-up mode is configured by the follow- ing settings: ? ieso = 1 (config<10>) internal/external switch over bit. ?scs = 0 . ?f osc configured for lp, xt or hs mode. two-speed start-up mode is entered after: ? power-on reset (por) and, if enabled, after pwrt has expired, or ? wake-up from sleep. if the external clock oscillator is configured to be any- thing other than lp, xt or hs mode, then two-speed start-up is disabled. this is because the external clock oscillator does not require any stabilization time after por or an exit from sleep. 3.6.2 two-speed start-up sequence 1. wake-up from power-on reset or sleep. 2. instructions begin execution by the internal oscillator at the frequency set in the ircf bits (in the osccon register. 3. ost enabled to count 1024 clock cycles. 4. ost timed out, wait for falling edge of the inter- nal oscillator. 5. osts is set. 6. system clock held low until the next falling edge of new clock (lp, xt or hs mode). 7. system clock is switched to external clock source. 3.6.3 checking external/internal clock status checking the state of the osts bit in the osccon register) will confirm if the pic16f785/hv785 is run- ning from the external clock source as defined by the f osc bits in the configuration word (config) or the internal oscillator. note: any automatic clock switch, which may occur from two-speed start-up or fail-safe clock monitor, does not update the scs bit. the user can monitor the osts (osccon<3>) to determine the current system clock source. note: executing a sleep instruction will abort the oscillator start-up time and will cause the osts bit in the osccon register to remain clear.
? 2008 microchip technology inc. ds41249e-page 31 pic16f785/hv785 figure 3-7: two-speed start-up 3.7 fail-safe clock monitor the fail-safe clock monitor (fscm) is designed to allow the device to continue to operate in the event of an oscillator failure. the fscm can detect oscillator failure at any point after the device has exited a reset or sleep condition and the oscillator start-up timer (ost) has expired. figure 3-8: fscm block diagram the fscm function is enabled by setting the fcmen bit in configuration word (config). it is applicable to all external clock options (lp, xt, hs, ec, rc or i/o modes). in the event of an external clock failure, the fscm will set the osfif bit in the pir1 register and generate an oscillator fail interrupt if the osfie bit in the pie1 reg- ister is set. the device will then switch the system clock to the internal oscillator. the system clock will continue to come from the internal oscillator unless the external clock recovers and the fail-safe condition is exited. the frequency of the internal oscillator will depend upon the value contained in the ircf bits (osccon<6:4>). upon entering the fail-safe condi- tion, the osts bit in the osccon register is automat- ically cleared to reflect that the internal oscillator is active and the wdt is cleared. the scs bit in the osc- con register is not updated. enabling fscm does not affect the lts bit. the fscm sample clock is generated by dividing the lfintosc clock by 64. this will allow enough time between fscm sample clocks for a system clock edge to occur. figure 3-8 shows the fscm block diagram. on the rising edge of the sample clock, the monitoring latch (cm = 0 ) will be cleared. on a falling edge of the primary system clock, the monitoring latch will be set (cm = 1 ). in the event that a falling edge of the sample clock occurs, and the monitoring latch is not set, a clock failure has been detected. the assigned internal oscillator is enabled when fscm is enabled as reflected by the ircf bits. q1 q2 q3 q4 q1 q2 q3 q4 q1 0 1 1022 1023 pc pc + 1 pc + 2 t ost t intosc osc1 osc2 program counter system clock primary lfintosc 64 s c q 31 khz (~32 s) 488 hz (~2 ms) clock monitor latch (cm) (edge-triggered) clock failure detected oscillator clock q note: two-speed start-up is automatically enabled when the fail-safe clock monitor mode is enabled.
pic16f785/hv785 ds41249e-page 32 ? 2008 microchip technology inc. 3.7.1 fail-safe condition clearing the fail-safe condition is cleared after a reset, the execution of a sleep instruction, or a modification of the scs bit. while in fail-safe condition, the pic16f785/hv785 uses the internal oscillator as the system clock source. the ircf bits in the osccon register can be modified to adjust the internal oscillator frequency without exiting the fail-safe condition. the fail-safe condition must be cleared before the osfif flag can be cleared. figure 3-9: fscm timing diagram 3.7.2 reset or wake-up from sleep the fscm is designed to detect oscillator failure at any point after the device has exited a reset or sleep condition and the oscillator start-up timer (ost) has expired. if the external clock is ec or rc mode, monitoring will begin immediately following these events. for lp, xt or hs mode, the external oscillator may require a start-up time considerably longer than the fscm sample clock time; a false clock failure may be detected (see figure 3-9). to prevent this, the internal oscillator is automatically configured as the system clock and functions until the external clock is stable (the ost has timed out). this is identical to two-speed start-up mode. once the external oscillator is stable, the lfintosc returns to its role as the fscm source. oscfif cm output system clock output sample clock failure detected oscillator failure note: the system clock is normally at a much higher frequency than the sample clock. the relative frequencies in this example have been chosen for clarity. (q ) cm test cm test cm test note: due to the wide range of oscillator start-up times, the fail-safe circuit is not active during oscillator start-up (i.e., after exiting reset or sleep). after an appropriate amount of time, the user should check the osts bit in the osccon register to ver- ify the oscillator start-up and system clock switchover has successfully completed.
? 2008 microchip technology inc. ds41249e-page 33 pic16f785/hv785 register 3-2: osccon: oscillator co ntrol register u-0 r/w-1 r/w-1 r/w-0 r-q r-0 r-0 r/w-0 ? ircf2 ircf1 ircf0 osts (1) hts lts scs bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6-4 ircf<2:0>: internal oscillator frequency select bits 000 =31khz 001 =125khz 010 =250khz 011 =500khz 100 =1mhz 101 =2mhz 110 =4mhz 111 =8mhz bit 3 osts: oscillator start-up time-out status bit (1) 1 = device is running from the external system clock defined by fosc<2:0> 0 = device is running from the internal system clock (hfintosc or lfintosc) bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 hts: hfintosc (high frequency ? 8 mhz to 125 khz) status bit 1 = hfintosc is stable 0 = hfintosc is not stable bit 1 lts: lfintosc (low frequency ? 31 khz) stable bit 1 = lfintosc is stable 0 = lfintosc is not stable bit 0 scs: system clock select bit 1 = internal oscillator is used for system clock 0 = clock source defined by fosc<2:0> note 1: bit resets to ? 0 ? with two-speed start-up and lp, xt or hs selected as the oscillator mode or fail-safe mode is enabled, otherwise this bit resets to ? 1 ?
pic16f785/hv785 ds41249e-page 34 ? 2008 microchip technology inc. table 3-4: summary of registers associated with clock sources name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets config cpd cp mclre pwrte wdte fosc2 fosc1 fosc0 ? ? osccon ? ircf2 ircf1 ircf0 osts hts lts scs -110 q000 -110 q000 osctune ? ? ? tun4 tun3 tun2 tun1 tun0 ---0 0000 ---u uuuu pie1 eeie adie ccp1ie c2ie c1ie osfie tmr2ie tmr1ie 0000 0000 0000 0000 pir1 eeif adif ccp1if c2if c1if osfif tmr2if tmr1if 0000 0000 0000 0000 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?, q = value depends on condition. shaded cells are not used by oscillators. note 1: see register 15.2 for operation of all configuration word bits.
? 2008 microchip technology inc. ds41249e-page 35 pic16f785/hv785 4.0 i/o ports there are seventeen general purpose i/o pins and one input only pin available. depending on which peripher- als are enabled, some or all of the pins may not be available as general purpose i/o. in general, when a peripheral is enabled, the associated pin may not be used as a general purpose i/o pin. 4.1 porta and trisa registers porta is a 6-bit wide, bidirectional port. the corre- sponding data direction register is trisa (register 4-2). setting a trisa bit (= 1 ) will make the corresponding porta pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisa bit (= 0 ) will make the corresponding porta pin an output (i.e., put the contents of the output latch on the selected pin). the exception is ra3, which is input only and its tris bit will always read as ? 1 ?. example 4-1 shows how to initialize porta. reading the porta register (register 4-1) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read; this value is modified and then written to the port data latch. ra3 reads ? 0 ? when mclre = 1 . the trisa register controls the direction of the porta pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. i/o pins configured as analog inputs always read ? 0 ?. when ra1 is configured as a voltage reference output, the ra1 digital output driver will automatically be disabled while not affecting the trisa<1> value. example 4-1: initializing porta register 4-1: porta: porta register note: the ansel0 (91h) register must be initial- ized to configure an analog channel as a digital input. pins configured as analog inputs will read ? 0 ?. bcf status,rp0 ;bank 0 bcf status,rp1 ; clrf porta ;init porta movlw f8h ;set ra<2:0> to andwf ansel0,f ; digital i/o bsf status,rp0 ;bank 1 movlw 0ch ;set ra<3:2> as inputs movwf trisa ; and set ra<5:4,1:0> ; as outputs bcf status,rp0 ;bank 0 u-0 u-0 r/w-x r/w-x (1) r/w-x r/w-x (1) r/w-x (1) r/w-x (1) ? ? ra5 ra4 ra3 ra2 ra1 ra0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented : read as ? 0 ? bit 5-0 ra<5:0> : porta i/o pin bits 1 = port pin is greater than v ih 0 = port pin is less than v il note 1: data latches are unknown after a por, but each port bit reads ? 0 ? when the corresponding analog select bit is ? 1 ? (see register 12-1).
pic16f785/hv785 ds41249e-page 36 ? 2008 microchip technology inc. register 4-2: trisa: porta tri-state register 4.2 additional pin functions every porta pin on the pic16f785/hv785 has an interrupt-on-change option and a weak pull-up option. the next three sections describe these functions. 4.2.1 weak pull-ups each of the porta pins has an individually configurable internal weak pull-up. control bits wpuax enable or disable each pull-up. refer to register 4-3. each weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on a power-on reset by the rapu bit in the (option register. the weak pull-up on ra3 is automatically enabled when ra3 is configured as mclr . register 4-3: wpua: weak pull-up register u-0 u-0 r/w-1 r/w-1 r-1 r/w-1 r/w-1 r/w-1 ? ? trisa5 (2) trisa4 (2) trisa3 (1) trisa2 trisa1 trisa0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-0 trisa<5:0>: porta tri-state control bit (1), (2) 1 = porta pin configured as an input (tri-stated) 0 = porta pin configured as an output bit 0 c: carry/borrow bit ( addwf , addlw, sublw, subwf instructions) (1) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: trisa<3> always reads ? 1 ?. 2: trisa<5:4> always reads ? 1 ? in xt, hs and lp osc modes. u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? wpua5 (4) wpua4 (4) wpua3 (3) wpua2 wpua1 wpua0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-0 wpua<5:0>: weak pull-up register bits 1 = pull-up enabled 0 = pull-up disabled note 1: global rapu must be enabled for individual pull-ups to be enabled. 2: the weak pull-up device is automatically disabled if the pin is in output mode (trisa = 0 ). 3: the ra3 pull-up is automatically enabled when configured as mclr in the configuration word. 4: wpua<5:4> always reads ? 1 ? in xt, hs and lp osc modes.
? 2008 microchip technology inc. ds41249e-page 37 pic16f785/hv785 4.2.2 interrupt-on-change each of the porta pins is individually configurable as an interrupt-on-change pin. control bits iocax enable or disable the interrupt function for each pin. refer to register 4-4. the interrupt-on-change is disabled on a power-on reset. for enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of porta. the ?mismatch? outputs of the last read are or?d together to set, the porta change interrupt flag bit (raif) in the intcon register (register 2-3). this interrupt can wake the device from sleep. the user, in the interrupt service routine, clears the inter- rupt by: a) any read or write of porta. this will end the mismatch condition, then, b) clear the flag bit raif. a mismatch condition will continue to set flag bit raif. reading porta will end the mismatch condition and allow flag bit raif to be cleared. the latch holding the last read value is neither affected by an mclr nor bor reset. after these resets, the raif flag will continue to be set if a mismatch is present. register 4-4: ioca: interrupt-on-change porta register note: if a change on the i/o pin should occur when the read operation is being executed (start of the q2 cycle), then the raif interrupt flag may not get set. u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ?ioca5 (2) ioca4 (2) ioca3 ioca2 ioca1 ioca0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-0 ioca<5:0>: interrupt-on-change porta control bits (2) 1 = interrupt-on-change enabled 0 = interrupt-on-change disabled note 1: global interrupt enable (gie) must be enabled for individual interrupts to be recognized. 2: ioca<5:4> always reads ? 1 ? in xt, hs and lp osc modes.
pic16f785/hv785 ds41249e-page 38 ? 2008 microchip technology inc. 4.2.3 porta pin descriptions and diagrams each porta pin is multiplexed with other functions. the pins and their combined functions are briefly described here. for specific information about individ- ual functions such as the comparator or the a/d, refer to the appropriate section in this data sheet. 4.2.3.1 ra0/an0/c1in+/icspdat figure 4-1 shows the diagram for this pin. the ra0 pin is configurable to function as one of the following: ? general purpose i/o ? analog input for the a/d ? analog input to comparator 1 ? in-circuit serial programming ? data figure 4-1: block diagram of ra0 4.2.3.2 ra1/an1/c12in0-/v ref /icspclk figure 4-1 shows the diagram for this pin. the ra1 pin is configurable to function as one of the following: ? general purpose i/o ? analog input for the a/d ? analog input to comparators 1 and 2 ? voltage reference input for the a/d ? buffered or unbuffered voltage reference output ? in-circuit serial programming clock figure 4-2: block diagram of ra1 i/o pin v dd v ss d q ck q d q ck q d q ck q d q ck q v dd weak data bus wr wpua rd wpua rd porta rd porta wr porta wr trisa rd trisa wr ioca rd ioca to comparator to a/d converter ans0 rapu ans0 d en q d en q d en q q1 q3 interrupt-on- change i/o pin v dd v ss d q ck q d q ck q d q ck q d q ck q v dd weak data bus wr wpua rd wpua rd porta wr porta wr trisa rd trisa wr ioca rd ioca interrupt-on- to comparators to a/d converter rapu ans1 cvroe vroe*vren vr out rd porta d en q d en q d en q q1 q3 change
? 2008 microchip technology inc. ds41249e-page 39 pic16f785/hv785 4.2.3.3 ra2/an2/t0cki/int/c1out figure 4-3 shows the diagram for this pin. the ra2 pin is configurable to function as one of the following: ? general purpose i/o ? analog input for the a/d ? clock input for tmr0 ? external edge triggered interrupt ? digital output from comparator 1 figure 4-3: blo ck diagram of ra2 4.2.3.4 ra3/mclr /v pp figure 4-4 shows the diagram for this pin. the ra3 pin is configurable to function as one of the following: ? general purpose input ? master clear reset with weak pull-up figure 4-4: block diagram of ra3 i/o pin v dd v ss d q ck q d q ck q d q ck q d q ck q v dd weak ans2 data bus wr wpua rd wpua rd porta wr porta wr trisa rd trisa wr ioca rd ioca to a/d converter 0 1 to i n t to t m r 0 ans2 rapu interrupt-on- change c1out c1oe d en q d en q d en q q1 q3 rd porta input v ss d q ck q rd porta wr ioca rd ioca reset mclre rd trisa v ss mclre v dd weak mclre interrupt-on- change pin d en q d en q d en q q1 q3 rd porta d q ck q data bus wr wpua rd wpua rapu
pic16f785/hv785 ds41249e-page 40 ? 2008 microchip technology inc. 4.2.3.5 ra4/an3/t1g/osc2/clkout figure 4-5 shows the diagram for this pin. the ra4 pin is configurable to function as one of the following: ? general purpose i/o ? analog input for the a/d ? tmr1 gate input ? crystal/resonator connection ? clock output figure 4-5: blo ck diagram of ra4 4.2.3.6 ra5/t1cki/osc1/clkin figure 4-6 shows the diagram for this pin. the ra5 pin is configurable to function as one of the following: ? general purpose i/o ? tmr1 clock input ? crystal/resonator connection ? clock input figure 4-6: block diagram of ra5 i/o pin v dd v ss d q ck q d q ck q d q ck q d q ck q v dd weak data bus wr wpua rd wpua rd porta wr porta wr trisa rd trisa wr ioca rd ioca f osc /4 to a/d converter oscillator circuit osc1 clkout 0 1 enable ans3 rapu to t 1 g intosc/ rc/ec (2) clk (1) modes clkout enable note 1: clk modes are xt, hs, lp, lptmr1 and clkout enable. 2: with clkout option. interrupt-on- change ans3 d en q d en q d en q q1 q3 rd porta s i/o pin v dd v ss d q ck q d q ck q d q ck q d q ck q v dd weak data bus wr wpua rd wpua rd porta wr porta wr trisa rd trisa wr ioca rd ioca to tmr1 or clkgen intosc mode intosc mode rapu osc2 (2) note 1: clk modes are xt, hs, lp and lptmr1. 2: when using timer1 with lp oscillator, the schmitt trigger is bypassed. clk modes (1) interrupt-on- change oscillator circuit d en q d en q d en q q1 q3 rd porta s
? 2008 microchip technology inc. ds41249e-page 41 pic16f785/hv785 table 4-1: summary of regist ers associated with porta name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets ansel0 ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 1111 1111 1111 1111 cm1con0 c1on c1out c1oe c1pol c1sp c1r c1ch1 c1ch0 0000 0000 0000 0000 cm2con1 mc1out mc2out ? ? ? ?t1gss c2sync 00-- --10 00-- --10 intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 ioca ? ? ioca5 ioca4 ioca3 ioca2 ioca1 ioca0 --00 0000 --00 0000 option_reg rapu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --xx xxxx --uu uuuu refcon ? ? bgst vrbb vren vroe cvroe ? --00 000- --00 000- t1con t1ginv tmr1ge t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 0000 0000 trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 wpua ? ? wpua5 wpua4 wpua3 wpua2 wpua1 wpua0 --11 1111 --11 1111 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by porta.
pic16f785/hv785 ds41249e-page 42 ? 2008 microchip technology inc. 4.3 portb and trisb registers portb is a 4-bit wide, bidirectional port. the corre- sponding data direction register is trisb (register 4- 6). setting a trisb bit (= 1 ) will make the correspond- ing portb pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisb bit (= 0 ) will make the corresponding portb pin an output (i.e., put the contents of the output latch on the selected pin). example 4-2 shows how to initial- ize portb. reading the portb register (register 4-5) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then writ- ten to the port data latch. pin rb6 is an open drain output. all other portb pins have full cmos output drivers. the trisb register controls the direction of the portb pins, even when they are being used as ana- log inputs. the user must ensure the bits in the trisb register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ?. example 4-2: initializing portb register 4-5: portb: portb register register 4-6: trisb: port b tri-state register note: the ansel1 (93h) register must be initial- ized to configure an analog channel as a digital input. pins configured as analog inputs will read ? 0 ?. bcf status,rp0 ;bank 0 bcf status,rp1 ; clrf portb ;init portb bsf status,rp0 ;bank 1 bcf ansel1,2 ;digital i/o - rb4 bcf ansel1,3 ;digital i/o - rb5 movlw 30h ;set rb<5:4> as inputs movwf trisb ;and set rb<7:6> ;as outputs bcf status,rp0 ;bank 0 r/w-x r/w-x r/w-x (1) r/w-x (1) u-0 u-0 u-0 u-0 rb7 rb6 rb5 rb4 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 rb<7:4>: portb general purpose i/o pin bits 1 = port pin is greater than v ih 0 = port pin is less than v il bit 3-0 unimplemented : read as ? 0 ? note 1: data latches are unknown after a por, but each port bit reads ? 0 ? when the corresponding analog select bit is ? 1 ? (see register 12-2 on page 82). r/w-1 r/w-1 r/w-1 r/w-1 u-0 u-0 u-0 u-0 trisb7 trisb6 trisb5 trisb4 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 trisb<7:4>: portb tri-state control bits 1 = portb pin configured as an input (tri-stated) 0 = portb pin configured as an output bit 3-0 unimplemented : read as ? 0 ?
? 2008 microchip technology inc. ds41249e-page 43 pic16f785/hv785 4.3.1 portb pin descriptions and diagrams each portb pin is multiplexed with other functions. the pins and their combined functions are briefly described here. for specific information about individ- ual functions such as the pwm, operational amplifier, or the a/d, refer to the appropriate section in this data sheet. 4.3.1.1 rb4/an10/op2- the rb4/an10/op2- pin is configurable to function as one of the following: ? general purpose i/o ? analog input to the a/d ? analog input to op amp 2 4.3.1.2 rb5/an11/op2+ the rb5/an11/op2+ pin is configurable to function as one of the following: ? general purpose i/o ? analog input to the a/d ? analog input to op amp 2 figure 4-7: block diagram of rb4 and rb5 4.3.1.3 rb6 the rb6 pin is configurable to function as the following: ? open drain general purpose i/o figure 4-8: block diagram of rb6 4.3.1.4 rb7/sync the rb7/sync pin is configurable to function as one of the following: ? general purpose i/o ? pwm synchronization input and output figure 4-9: block diagram of rb7 i/o pin v dd v ss d q ck q d q ck q data bus wr portb wr trisb rd trisb to a/d converter rd portb ans10 (rb4) ans11 (rb5) to op amp 2 d en q i/o pin v ss d q ck q d q ck q data bus wr portb wr trisb rd trisb n v ss rd portb d en q i/o pin v dd v ss d q ck q d q ck q data bus wr portb wr trisb rd trisb 0 1 sync out pwm master to pwm sync input ph1en ph2en rd portb d en q
pic16f785/hv785 ds41249e-page 44 ? 2008 microchip technology inc. table 4-2: summary of registers associated with portb name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets ansel1 ? ? ? ?ans11ans10 ans9 ans8 ---- 1111 ---- 1111 opa2con opaon ? ? ? ? ? ? ? 0--- ---- 0--- ---- portb rb7 rb6 rb5 rb4 ? ? ? ? xxxx ---- uuuu ---- pwmcon0 prsen pasen blank2 blank1 sync1 sync0 ph2en ph1en 0000 0000 0000 0000 trisb trisb7 trisb6 trisb5 trisb4 ? ? ? ? 1111 ---- 1111 ---- legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by portb.
? 2008 microchip technology inc. ds41249e-page 45 pic16f785/hv785 4.4 portc and trisc registers portc is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisc (register 4- 8). setting a trisc bit (= 1 ) will make the correspond- ing portc pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisc bit (= 0 ) will make the corresponding portc pin an output (i.e., put the contents of the output latch on the selected pin). example 4-3 shows how to initial- ize portc. reading the portc register (register 4-7) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch. the trisc register controls the direction of the portc pins, even when they are being used as analog inputs. the user must ensure the bits in the trisc register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ? . when rc4 or rc5 is configured as an op amp output, the corresponding rc4 or rc5 digital output driver will automatically be disabled regardless of the trisc<4> or trisc<5> value. example 4-3: initializing portc register 4-7: port c: portc register register 4-8: trisc: po rtc tri-state register note: the ansel0 (91h) and ansel1 (93h) registers must be initialized to configure an analog channel as a digital input. pins configured as analog inputs will read ? 0 ?. bcf status,rp0 ;bank 0 bcf status,rp1 clrf portc ;init portc bsf status,rp0 ;bank 1 clrf ansel0 ;digital i/o clrf ansel1 ;digital i/o movlw 0ch ;set rc<3:2> as inputs movwf trisc ; and set rc<5:4,1:0> ; as outputs bcf status,rp0 ;bank 0 r/w-x (1) r/w-x (1) r/w-x r/w-x r/w-x (1) r/w-x (1) r/w-x (1) r/w-x (1) rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 rc<7:0>: portc general purpose i/o pin bits 1 = port pin is greater than v ih 0 = port pin is less than v il note 1: data latches are unknown after a por, but each port bit reads ? 0 ? when the corresponding analog select bit is ? 1 ? (see registers 12-1 and 12-2 on page 82 ). r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 trisc<7:0>: portc tri-state control bits 1 = portc pin configured as an input (tri-stated) 0 = portc pin configured as an output
pic16f785/hv785 ds41249e-page 46 ? 2008 microchip technology inc. 4.4.1 portc pin descriptions and diagrams each portc pin is multiplexed with other functions. the pins and their combined functions are briefly described here. for specific information about individ- ual functions such as the comparator or the a/d, refer to the appropriate section in this data sheet. 4.4.1.1 rc0/an4/c2in+ the rc0 is configurable to function as one of the following: ? general purpose i/o ? analog input for the a/d converter ? non-inverting input to comparator 2 4.4.1.2 rc6/an8/op1- the rc6/an8/op1- pin is configurable to function as one of the following: ? general purpose i/o ? analog input for the a/d ? inverting input for op amp 1 4.4.1.3 rc7/an9/op1+ the rc7/an9/op1+ pin is configurable to function as one of the following: ? general purpose i/o ? analog input for the a/d ? non-inverting input for op amp 1 figure 4-10: blo ck diagram of rc0, rc6 and rc7 4.4.1.4 rc1/an5/c12in1-/ph1 the rc1 is configurable to function as one of the following: ? general purpose i/o ? analog input for the a/d converter ? analog input to comparators 1 and 2 ? digital output from the two-phase pwm figure 4-11: block diagram of rc1 i/o pin v dd v ss d q ck q d q ck q data bus wr portc wr trisc rd trisc to a/d converter ans4 (rc0) ans8 (rc6) to comparators (rc0) to op amp1 (rc6, rc7) rd portc d en q ans9 (rc7) i/o pin v dd v ss d q ck q d q ck q data bus wr portc wr trisc rd trisc to a / d c o n v e r t e r ans5 to comparators 0 1 ph1 ph1en rd portc d en q
? 2008 microchip technology inc. ds41249e-page 47 pic16f785/hv785 4.4.1.5 rc2/an6/c12in2-/op2 the rc2 is configurable to function as one of the following: ? general purpose i/o ? analog input for the a/d converter ? analog input to comparators 1 and 2 ? analog output from op amp 2 4.4.1.6 rc3/an7/c12in3-/op1 the rc3 is configurable to function as one of the following: ? general purpose i/o ? analog input for the a/d converter ? analog input to comparators 1 and 2 ? analog output for op amp 1 figure 4-12: block diagram of rc2 and rc3 4.4.1.7 rc4/c2out/ph2 the rc4 is configurable to function as one of the following: ? general purpose i/o ? digital output from comparator 2 ? digital output from the two-phase pwm figure 4-13: block diagram of rc4 i/o pin v dd v ss d q ck q d q ck q data bus wr portc wr trisc rd trisc to a/d converter ans6 (rc2) ans7 (rc3) to comparators op amp out opaon rd portc d en q i/o pin v dd v ss d q ck q d q ck q data bus wr portc wr trisc rd trisc 0 1 ph2 0 1 c2out ph2en c2oe rd portc d en q
pic16f785/hv785 ds41249e-page 48 ? 2008 microchip technology inc. 4.4.1.8 rc5/ccp1 the rc5 is configurable to function as one of the following: ? general purpose i/o ? digital input for the capture/compare ? digital output for the ccp figure 4-14: block diagram of rc5 table 4-3: summary of registers associated with portc i/o pin v dd v ss d q ck q d q ck q data bus wr portc wr trisc rd trisc 0 1 ccp out ccp1con<3> ccp1con<1> to ccp capture input rd portc d en q ccp1con<2> name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets ansel1 ? ? ? ? ans11 ans10 ans9 ans8 ---- 1111 ---- 1111 ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 0000 0000 0000 0000 opa1con opaon ? ? ? ? ? ? ? 0--- ---- 0--- ---- opa2con opaon ? ? ? ? ? ? ? 0--- ---- 0--- ---- portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu pwmcon0 prsen pasen blank2 blank1 sync1 sync0 ph2en ph1en 0000 0000 0000 0000 trisc trisc7 trisc6 trisc5 trisc 4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by portc.
? 2008 microchip technology inc. ds41249e-page 49 pic16f785/hv785 5.0 timer0 module the timer0 module timer/counter has the following features: ? 8-bit timer/counter ? readable and writable ? 8-bit software programmable prescaler ? internal or external clock select ? interrupt on overflow from ffh to 00h ? edge select for external clock figure 5-1 is a block diagram of the timer0 module and the prescaler shared with the wdt. 5.1 timer0 operation timer mode is selected by clearing the t0cs bit of the option register. in timer mode, the timer0 module will increment every instruction cycle (without pres- caler). if tmr0 is written, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting the t0cs bit of the option register. in this mode, the timer0 module will increment either on every rising or falling edge of pin ra2/an2/t0cki/int/c1out. the incrementing edge is determined by the source edge (t0se) control bit of the option register. clearing the t0se bit selects the rising edge. 5.2 timer0 interrupt a timer0 interrupt is generated when the tmr0 register timer/counter overflows from ffh to 00h. this overflow sets the t0if bit of the intcon register. the interrupt can be masked by clearing the t0ie bit of the intcon register. the t0if bit must be cleared in soft- ware by the timer0 module interrupt service routine before re-enabling this interrupt. the timer0 interrupt cannot wake the processor from sleep since the timer is shut-off during sleep. figure 5-1: block di agram of the timer0/wdt prescaler note 1: counter mode has specific external clock requirements. 2: the ansel0 (91h) register must be ini- tialized to configure an analog channel as a digital input. pins configured as analog inputs will read ? 0 ?. t0se (1) clkout tmr0 watchdog timer wdt time-out ps<0:2> (1) wdte data bus set flag bit t0if on overflow t0cs (1) note 1: t0se, t0cs, psa, ps<2:0> are bits in the option_reg (see register 2.2.2.3). 2: wdtps<3:0> are bits in the wdtc on register (see register 15-2). 0 1 0 1 0 1 sync 2 cycles 8 8 8-bit prescaler 0 1 (= f osc /4) psa (1) psa (1) psa (1) 16-bit prescaler 16 wdtps<3:0> (2) 31 khz intrc swdten ra2/an2/t0cki/int/c1out
pic16f785/hv785 ds41249e-page 50 ? 2008 microchip technology inc. 5.3 using timer0 with an external clock when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki, with the internal phase clocks, is accom- plished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks. therefore, it is necessary for t0cki to be high for at least 2t osc (and a small rc delay of 20 ns) and low for at least 2t osc (and a small rc delay of 20 ns). refer to the electrical specification of the desired device. 5.4 prescaler an 8-bit counter is available as a prescaler for the timer0 module, or as a postscaler for the watchdog timer. for simplicity, this counter will be referred to as ?prescaler? throughout this data sheet. the prescaler assignment is controlled in software by the control bit psa of the option register. clearing the psa bit will assign the prescaler to timer0. prescale values are selectable via the ps<2:0> bits of the option regis- ter. the prescaler is not readable or writable. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf 1, movwf 1, bsf 1,x....etc. ) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the watchdog timer. 5.4.1 switching prescaler assignment the prescaler assignment is fully under software control (i.e., it can be changed ?on the fly? during program execution). to avoid an unintended device reset, the following instruction sequence (example 5- 1 and example 5-2) must be executed when changing the prescaler assignment between timer0 and wdt. example 5-1: changing prescaler (timer0 wdt) to change prescaler from the wdt to the tmr0 module, use the sequence shown in example 5-2. this precaution must be taken even if the wdt is disabled. example 5-2: changing prescaler (wdt timer0) table 5-1: registers associated with timer0 bcf status,rp0 ;bank 0 bcf status,rp1 ; clrwdt ;clear wdt clrf tmr0 ;clear tmr0 and ; prescaler bsf status,rp0 ;bank 1 movlw b?00101111? ;required if desired movwf option_reg ; ps2:ps0 is clrwdt ; 000 or 001 ; movlw b?00101xxx? ;set postscaler to movwf option_reg ; desired wdt rate bcf status,rp0 ;bank 0 clrwdt ;clear wdt and ; prescaler bsf status,rp0 ;bank 1 bcf status,rp1 ; movlw b?xxxx0xxx? ;select tmr0, ; prescale, and ; clock source movwf option_reg ; bcf status,rp0 ;bank 0 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets ansel0 ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 1111 1111 1111 1111 intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 option_reg rapu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 tmr0 timer0 module register xxxx xxxx uuuu uuuu trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 legend: ? = unimplemented locations, read as ? 0 ?, u = unchanged, x = unknown. shaded cells are not used by the timer0 module.
? 2008 microchip technology inc. ds41249e-page 51 pic16f785/hv785 6.0 timer1 module with gate control the timer1 module is the 16-bit counter of the pic16f785/hv785. figure 6-1 shows the basic block diagram of the timer1 module. timer1 has the follow- ing features: ? 16-bit timer/counter (tmr1h:tmr1l) ? readable and writable ? internal or external clock selection ? synchronous or asynchronous operation ? interrupt on overflow from ffffh to 0000h ? wake-up upon overflow (asynchronous mode) ? optional external enable input: - selectable gate source; t1g or c2 output (t1gss) - selectable gate polarity (t1ginv) ? optional lp oscillator the timer1 control register (t1con), shown in register 6-1, is used to enable/disable timer1 and select the various features of the timer1 module. figure 6-1: timer1 on the pic16f785/hv785 block diagram tmr1h tmr1l oscillator t1sync tmr1cs t1ckps<1:0> sleep input f osc /4 internal clock prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 set flag bit tmr1if on overflow tmr1 (1) tmr1on tmr1ge tmr1on tmr1ge intosc t1oscen without clkout * 1 0 syncc2out (2) t1gss t1ginv to c2 comparator module tmr1 clock * st buffer is low power type when using lp osc, or high-speed type when using t1cki. note 1: timer1 increments on the rising edge. 2: syncc2out is the synchronized output from comparator 2 (see figure 9-2 on 66). ra5/t1cki/osc1/clkin ra4/an3/t1g/osc2/clkout lp sleep d q en
pic16f785/hv785 ds41249e-page 52 ? 2008 microchip technology inc. 6.1 timer1 modes of operation timer1 can operate in one of three modes: ? 16-bit timer with prescaler ? 16-bit synchronous counter ? 16-bit asynchronous counter in timer mode, timer1 is incremented on every instruc- tion cycle. in counter mode, timer1 is incremented on the rising edge of the external clock input t1cki. in addition, the counter mode clock can be synchronized to the microcontroller system clock or run asynchronously. in counter and timer modules, the counter/timer clock can be gated by the timer1 gate, which can be selected as either the t1g pin or comparator 2 output. if an external clock oscillator is needed (and the microcontroller is using the lp oscillator or intosc without clkout), timer1 can use the lp oscillator as a clock source. 6.2 timer1 interrupt the timer1 register pair (tmr1h:tmr1l) increments to ffffh and rolls over to 0000h. when timer1 rolls over, the timer1 interrupt flag bit of the pir1 register is set. to enable the interrupt on rollover, you must set these bits: ? timer1 interrupt enable bit of the pie1 register ? peie bit of the intcon register ? gie bit of the intcon register the interrupt is cleared by clearing the tmr1if in the interrupt service routine. 6.3 timer1 prescaler timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. the t1ckps bits, of the t1con register, control the prescale counter. the prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to tmr1h or tmr1l. 6.4 timer1 gate timer1 gate source is software configurable to be t1g pin or the output of comparator 2. this allows the device to directly time external events using t1g or analog events using comparator 2. see cm2con1 (register 9-3) for selecting the timer1 gate source. this feature can simplify the software for a delta-sigma a/d converter and many other applications. for more information on delta-sigma a/d converters, see the microchip web site (www.microchip.com). timer1 gate can be inverted using the t1ginv bit of the t1con register, whether it originates from the t1g pin or comparator 2 output. this configures timer1 to measure either the active high or active low time between events. figure 6-2: timer1 incrementing edge note: in counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions. ? timer1 enabled after por reset ? write to tmr1h or tmr1l ? timer1 is disabled (tmr1on = 0 ) when t1cki is high then timer1 is enabled (tmr1on = 1 ) when t1cki is low. see figure 6-2. note: the tmr1h:tmr1l register pair and the tmr1if bit should be cleared before enabling interrupts. note: tmr1ge bit, of the t1con register, must be set to use either t1g or c2out as the timer1 gate source. see register 9-3 for more information on selecting the timer1 gate source. t1cki = 1 when tmr1 enabled t1cki = 0 when tmr1 enabled note 1: arrows indicate counter increments. 2: see note box in section 6.1 ?timer1 modes of operation? .
? 2008 microchip technology inc. ds41249e-page 53 pic16f785/hv785 register 6-1: t1con: time r1 control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 t1ginv (1) tmr1ge (2) t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 t1ginv: timer1 gate invert bit (1) 1 = timer1 gate is high true (see bit 6) 0 = timer1 gate is low true (see bit 6) bit 6 tmr1ge: timer1 gate enable bit (2) if tmr1on = 0 : this bit is ignored if tmr1on = 1 : 1 = timer1 is on if timer1 gate is true (see bit 7) 0 = timer1 is on independent of timer1 gate bit 5-4 t1ckps<1:0>: timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen: lp oscillator enable control bit if system clock is intosc without clkout or lp mode: 1 = lp oscillator is enabled for timer1 clock 0 = lp oscillator is off else: this bit is ignored bit 2 t1sync : timer1 external clock input synchronization control bit tmr1cs = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input tmr1cs = 0 : this bit is ignored. timer1 uses the internal clock. bit 1 tmr1cs: timer1 clock source select bit 1 = external clock from t1cki pin (on the rising edge) 0 = internal clock (f osc /4) bit 0 tmr1on: timer1 on bit 1 = enables timer1 0 = stops timer1 note 1: t1ginv bit inverts the timer1 gate logic, regardless of source. 2: tmr1ge bit must be set to use either t1g pin or c2out, as selected by t1gss bit (cm2con1<1>), as a timer1 gate source.
pic16f785/hv785 ds41249e-page 54 ? 2008 microchip technology inc. 6.5 timer1 operation in asynchronous counter mode if control bit t1sync of the t1con register is set, the external clock input is not synchronized. the timer con- tinues to increment asynchronous to the internal phase clocks. the timer will continue to run during sleep and can generate an interrupt on overflow, which will wake- up the processor. however, special precautions in software are needed to read/write the timer ( section 6.5.1 ?reading and writing timer1 in asynchronous counter mode? ). 6.5.1 reading and writing timer1 in asynchronous counter mode reading tmr1h or tmr1l while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). however, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. for writes, it is recommended that the user simply stop the timer and write the desired values. a write conten- tion may occur by writing to the timer registers, while the register is incrementing. this may produce an unpredictable value in the timer register. 6.6 timer1 oscillator a crystal oscillator circuit is built-in between pins osc1 (input) and osc2 (amplifier output). it is enabled by setting control bit t1oscen of the t1con register. the oscillator is a low power oscillator rated for 32.768 khz. it will continue to run during sleep. it is primarily intended for a 32.768 khz tuning fork crystal. the timer1 oscillator is shared with the system lp oscillator. thus, timer1 can use this mode only when the primary system clock is also the lp oscillator or is derived from the internal oscillator. as with the system lp oscillator, the user must provide a software time delay to ensure proper oscillator start-up. sleep mode will not disable the system clock when the system clock and timer1 share the lp oscillator. trisa<5> and trisa<4> bits are set when the timer1 oscillator is enabled. ra5 and ra4 read as ? 0 ? and trisa<5> and trisa<4> bits read as ? 1 ?. 6.7 timer1 operation during sleep timer1 can only operate during sleep when setup in asynchronous counter mode. in this mode, an external crystal or clock source can be used to increment the counter. to setup the timer to wake the device: ? timer1 of the t1con register must be on ? tmr1ie bit of the pie1 register must be set ? peie bit of the intcon register must be set the device will wake-up on an overflow. if the gie bit of the intcon register is set, the device will wake-up and jump to the interrupt service routine (0004h) on an overflow. if the gie bit is clear, execution will con- tinue with the next instruction. table 6-1: registers associated with timer1 note: the ansel0 (91h) register must be initial- ized to configure an analog channel as a digital input. pins configured as analog inputs will read ? 0 ?. note: the oscillator requires a start-up and stabilization time before use. thus, t1oscen should be set and a suitable delay observed prior to enabling timer1. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets ansel0 ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 1111 1111 1111 1111 cm2con1 mc1out mc2out ? ? ? ?t1gss c2sync 00-- --10 00-- --10 intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 pie1 eeie adie ccp1ie c2ie c1ie osfie tmr2ie tmr1ie 0000 0000 0000 0000 pir1 eeif adif ccp1if c2if c1if osfif tmr2if tmr1if 0000 0000 0000 0000 t1con t1ginv tmr1ge t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 uuuu uuuu tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu legend: ? x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by the timer1 module.
? 2008 microchip technology inc. ds41249e-page 55 pic16f785/hv785 7.0 timer2 module the timer2 module timer is an 8-bit timer with the following features: ? 8-bit timer (tmr2 register) ? 8-bit period register (pr2) ? readable and writable (both registers) ? software programmable prescaler (1:1, 1:4, 1:16) ? software programmable postscaler (1:1 to 1:16 by 1 ?s) ? interrupt on tmr2 match with pr2 timer2 has a control register shown in register 7-1. tmr2 can be shut-off by clearing control bit tmr2on, of the t2con register, to minimize power consump- tion. figure 7-1 is a simplified block diagram of the timer2 module. the prescaler and postscaler selection of timer2 are controlled by this register. 7.1 timer2 operation timer2 can be used as the pwm time base for the pwm mode of the ccp module. the tmr2 register is readable and writable, and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits t2ckps<1:0> of the t2con register. the match out- put of tmr2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr2 interrupt (latched in flag bit tmr2if), of the pir1 register. the prescaler and postscaler counters are cleared when any of the following occurs: ? a write to the tmr2 register ? a write to the t2con register ? any device reset (power-on reset, mclr reset, watchdog timer reset or brown-out reset) tmr2 is not cleared when t2con is written. register 7-1: t2con: timer2 control register u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6-3 toutps<3:0>: timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale ? ? ? 1111 = 1:16 postscale bit 2 tmr2on: timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps<1:0>: timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 note 1: for borrow , the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high-order or low-order bit of the source register.
pic16f785/hv785 ds41249e-page 56 ? 2008 microchip technology inc. 7.2 timer2 interrupt the timer2 module has an 8-bit period register, pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is initialized to ffh upon reset. figure 7-1: timer2 block diagram table 7-1: registers associated with timer2 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 pie1 eeie adie ccp1ie c2ie c1ie osfie tmr2ie tmr1ie 0000 0000 0000 0000 pir1 eeif adif ccp1if c2if c1if osfif tmr2if tmr1if 0000 0000 0000 0000 pr2 timer2 module period register 1111 1111 1111 1111 t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 tmr2 holding register for the 8-bit tmr2 register 0000 0000 0000 0000 legend: ? x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by the timer2 module. comparator tmr2 sets flag tmr2 output reset postscaler prescaler pr2 2 f osc /4 1:1 to 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if toutps<3:0> t2ckps<1:0>
? 2008 microchip technology inc. ds41249e-page 57 pic16f785/hv785 8.0 capture/compare/pwm (ccp) module the capture/compare/pwm (ccp) module contains a 16-bit register which can operate as a: ? 16-bit capture register ? 16-bit compare register ? pwm master/slave duty cycle register capture/compare/pwm register 1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp1con register controls the operation of ccp. the special event trigger is generated by a compare match and will clear both tmr1h and tmr1l registers. table 8-1: ccp mode ? timer resources required register 8-1: ccp1con: ccp operation register ccp mode timer resource capture timer1 compare timer1 pwm timer2 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ?. bit 5-4 dc1b<1:0>: pwm duty cycle least significant bits capture mode: unused compare mode: unused pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccpr1l. bit 3-0 ccp1m<3:0>: ccp mode select bits 0000 = capture/compare/pwm off (resets ccp module) 0001 = unused (reserved) 0010 = compare mode, toggle output on match (ccp1if bit is set) 0011 = unused (reserved) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, set output on match (ccp1if bit is set) 1001 = compare mode, clear output on match (ccp1if bit is set) 1010 = compare mode, generate software interrupt on match (ccp1if bit is set, ccp1 pin is unaffected) 1011 = compare mode, trigger special event (ccp1if bit is set; tmr1 is reset, and a/d conversion is started if the a/d module is enabled. ccp1 pin is unaffected.) 110x = pwm mode: ccp1 output is high true. 111x = pwm mode: ccp1 output is low true. note 1: for borrow , the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high-order or low-order bit of the source register.
pic16f785/hv785 ds41249e-page 58 ? 2008 microchip technology inc. 8.1 capture mode in capture mode, ccpr1h:ccpr1l captures the 16-bit value of the tmr1 register when an event occurs on pin rc5/ccp1. an event is defined as one of the following and is configured by ccp1con<3:0>: ? every falling edge ? every rising edge ? every 4th rising edge ? every 16th rising edge when a capture is made, the interrupt request flag bit ccp1if of the pir1 register is set. the interrupt flag must be cleared in software. if another capture occurs before the value in register ccpr1 is read, the old cap- tured value is overwritten by the new captured value. 8.1.1 ccp1 pin configuration in capture mode, the rc5/ccp1 pin should be config- ured as an input by setting the trisc<5> bit. figure 8-1: capture mode operation block diagram 8.1.2 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode for the ccp module to use the capture feature. in asynchronous counter mode, the capture operation may not work. 8.1.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep bit ccp1ie of the pie1 register clear to avoid false inter- rupts and should clear the flag bit ccp1if of the pir1 register following any such change in operating mode. 8.1.4 ccp prescaler there are four prescaler settings specified by bits ccp1m<3:0> of the ccp1con register. whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. example 8-1 shows the recom- mended method for switching between capture pres- calers. this example also clears the prescaler counter and will not generate the ?false? interrupt. example 8-1: changing between capture prescalers 8.2 compare mode in compare mode, the 16-bit ccpr1 register value is constantly compared against the tmr1 register pair value. when a match occurs, the rc5/ccp1 pin is: ? driven high ?driven low ? remains unchanged the action on the pin is based on the value of control bits ccp1m<3:0> of the ccp1con register. at the same time, interrupt flag bit ccp1if of the pir1 regis- ter is set. figure 8-2: compare mode operation block diagram note: if the rc5/ccp1 pin is configured as an output, a write to the port can cause a capture condition. ccpr1h ccpr1l tmr1h tmr1l set flag bit ccp1if (pir1<5>) capture enable q?s ccp1con<3:0> prescaler 1, 4, 16 and edge detect pin rc5/ccp1 clrf ccp1con ;turn ccp module off movlw new_capt_ps ;load the w reg with ; the new prescaler ; move value and ccp on movwf ccp1con ;load ccp1con with this ; value ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event trigger set flag bit ccp1if (pir1<5>) match trisc<5> ccp1con<3:0> mode select output enable pin special event trigger will: ? clear tmr1h and tmr1l registers ? not set interrupt flag bit tmr1f (pir1<0>) ? set the go/done bit (adcon0<1>) rc5/ccp1 4
? 2008 microchip technology inc. ds41249e-page 59 pic16f785/hv785 8.2.1 ccp1 pin configuration the user must configure the rc5/ccp1 pin as an output by clearing the trisc<5> bit. 8.2.2 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 8.2.3 software interrupt mode when generate software interrupt mode is chosen (ccp1m<3:0> = 1010 ), the rc5/ccp1 pin is not affected. the ccp1if bit of the pir1 register is set, causing a ccp interrupt (if enabled). see register 8-1. 8.2.4 special event trigger in this mode (ccp1m<3:0> = 1011 ), an internal hardware trigger is generated, which may be used to initiate an action. see register 8-1. the special event trigger output of the ccp occurs immediately upon a match between the tmr1h, tmr1l register pair and ccpr1h, ccpr1l register pair. the tmr1h, tmr1l register pair is not reset until the next rising edge of the tmr1 clock. this allows the ccpr1h, ccpr1l register pair to effectively provide a 16-bit programmable period register for timer1. the special event trigger output also starts an a/d conversion provided that the a/d module is enabled. table 8-2: registers associated with capture, compare, and timer1 note: clearing the ccp1con register will force the rc5/ccp1 compare output latch to the default low level. this is not the portc i/o data latch. note 1: the special event trigger from the ccp module will not set interrupt flag bit tmr1if (pir1<0>). 2: removing the match condition by chang- ing the contents of the ccpr1h and ccpr1l register pair between the clock edge that generates the special event trigger and the clock edge that generates the tmr1 reset, will preclude the reset from occurring. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 ccpr1l capture/compare/pwm register 1 low byte xxxx xxxx uuuu uuuu ccpr1h capture/compare/pwm register 1 high byte xxxx xxxx uuuu uuuu cm2con1 mc1out mc2out ? ? ? ?t1gss c2sync 00-- --10 00-- --10 intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 pie1 eeie adie ccp1ie c2ie c1ie osfie tmr2ie tmr1ie 0000 0000 0000 0000 pir1 eeif adif ccp1if c2if c1if osfif tmr2if tmr1if 0000 0000 0000 0000 t1con t1ginv tmr1ge t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 uuuu uuuu tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 --11 1111 --11 1111 legend: ? = unimplemented locations, read as ? 0 ?, u = unchanged, x = unknown. shaded cells are not used by the capture, compare or timer1 module.
pic16f785/hv785 ds41249e-page 60 ? 2008 microchip technology inc. 8.3 ccp pwm mode in pulse width modulation (pwm) mode, the ccp module produces up to a 10-bit resolution pwm output on the rc5/ccp1 pin. since the rc5/ccp1 pin is multiplexed with the portc data latch, the trisc<5> must be cleared to make the rc5/ccp1 pin an output. figure 8-3 shows a simplified block diagram of pwm operation. for a step by step procedure on how to set up the ccp module for pwm operation, see section 8.3.5 ?setup for pwm operation? . figure 8-3: simplified pwm block diagram the pwm output (figure 8-4) has a time base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/period). figure 8-4: ccp pwm output 8.3.1 pwm period the pwm period is specified by writing to the pr2 register. the pwm period can be calculated using the formula of equation 8-1. equation 8-1: pwm period pwm frequency is defined as 1/[pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: ?tmr2 is cleared ? the rc5/ccp1 pin is set. (exception: if pwm duty cycle = 0%, the pin will not be set) ? the pwm duty cycle is latched from ccpr1l into ccpr1h note: clearing the ccp1con register will force the pwm output latch to the default inactive levels. this is not the portc i/o data latch. ccpr1l ccpr1h (slave) comparator tmr2 pr2 (1) rq s duty cycle registers ccp1con<5:4> clear timer2, toggle pwm pin and latch duty cycle note 1: the 8-bit timer tmr2 register is concate- nated with the 2-bit internal q clock, or 2 bits of the prescaler, to create the 10-bit time base. trisc<5> rc5/ccp1 comparator period duty cycle tmr2 = 0 tmr2 = duty cycle tmr2 = pr2 note: the timer2 postscaler (see section 7.1 ?timer2 operation? ) is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different frequency than the pwm output. pwm period pr2 () 1 + [] 4t osc ? ? ? = (tmr2 prescale value)
? 2008 microchip technology inc. ds41249e-page 61 pic16f785/hv785 8.3.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr1l register and to the dc1b<1:0> bits of the ccp1con register. up to 10 bits of resolution is avail- able. the ccpr1l contains the eight msbs and the dc1b<1:0> contains the two lsbs. in pwm mode, ccpr1h is a read-only register. equation 8-2 is used to calculate the pwm duty cycle in time. equation 8-2: pwm duty cycle ccpr1l and dc1b<1:0> can be written to at any time, but the duty cycle value is not latched into ccpr1h until after a match between pr2 and tmr2 occurs (i.e. the period is complete). in pwm mode, ccpr1h is a read-only register. the ccpr1h register and a 2-bit internal latch are used to double buffer the pwm duty cycle. this double buffering is essential for glitchless pwm operation. because of the buffering, the module waits until the timer resets, instead of starting immediately. this means that enhanced pwm waveforms do not exactly match the standard pwm waveforms, but are instead offset by one full instruction cycle (4 t osc ). when the ccpr1h and 2-bit latch match tmr2, concatenated with an internal 2-bit q clock or 2 bits of the tmr2 prescaler, the rc5/ccp1 pin is cleared. the maximum pwm resolution is a function of pr2 as shown by equation 8-3. equation 8-3: pwm resolution table 8-3: example pwm frequencies and resolutions (f osc = 20 mhz) pwm duty cycle ccpr1l:ccp1con<5:4> () ? = t osc ? (tmr2 prescale value) note: if the pwm duty cycle value is longer than the pwm period, the assigned pwm pin(s) will remain unchanged. resolution 4pr2 1 + () [] log 2 () log ----------------------------------------- - bits = pwm frequency 1.22 khz (1) 4.88 khz (1) 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescale (1, 4, 16) 16 4 1 1 1 1 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 6.6 note 1: changing duty cycle will cause a glitch.
pic16f785/hv785 ds41249e-page 62 ? 2008 microchip technology inc. 8.3.3 operation in sleep mode in sleep mode, all clock sources are disabled. timer2 will not increment and the state of the module will not change. if the rc5/ccp1 pin is driving a value, it will continue to drive that value. when the device wakes up, it will continue from this state. 8.3.3.1 operation with fail-safe clock monitor if the fail-safe clock monitor is enabled, a clock failure will force the ccp to be clocked from the internal oscillator clock source, which may have a different clock frequency than the primary clock. see section 3.0 ?clock sources? for additional details. 8.3.4 effects of reset any reset will force all ports to input mode and the ccp registers to their reset states. 8.3.5 setup for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. configure the pwm pin (rc5/ccp1) as an input by setting the trisc<5> bit. 2. set the pwm period by loading the pr2 register. 3. configure the ccp module for the pwm mode by loading the ccp1con register with the appropriate values. 4. set the pwm duty cycle by loading the ccpr1l register and ccp1con<5:4> bits. 5. configure and start tmr2: ? clear the tmr2 interrupt flag bit by clearing the tmr2if bit of the pir1 register. ? set the tmr2 prescale value by loading the t2ckps bits of the t2con register. ? enable timer2 by setting the tmr2on bit of the t2con register. 6. enable pwm output after a new pwm cycle has started: ? wait until tmr2 overflows (tmr2if bit is set). ? enable the rc5/ccp1 pin output by clearing the trisc<5> bit. table 8-4: registers associated with ccp and timer2 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 0000 0000 0000 0000 ccpr1l capture/compare/pwm register 1 low byte xxxx xxxx uuuu uuuu ccpr1h capture/compare/pwm register 1 high byte xxxx xxxx uuuu uuuu intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 pie1 eeie adie ccp1ie c2ie c1ie osfie tmr2ie tmr1ie 0000 0000 0000 0000 pir1 eeif adif ccp1if c2if c1if osfif tmr2if tmr1if 0000 0000 0000 0000 pr2 timer2 module period register 1111 1111 1111 1111 t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 tmr2 timer2 module register 0000 0000 0000 0000 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 --11 1111 --11 1111 legend: ? = unimplemented locations, read as ? 0 ?, u = unchanged, x = unknown. shaded cells are not used by the ccp or timer2 modules.
? 2008 microchip technology inc. ds41249e-page 63 pic16f785/hv785 9.0 comparator module the comparator module has two separate voltage comparators: comparator 1 (c1) and comparator 2 (c2). each comparator offers the following list of features: ? control and configuration register ? comparator output available externally ? programmable output polarity ? interrupt-on-change flags ? wake-up from sleep ? configurable as feedback input to the pwm ? programmable four input multiplexer ? programmable two input reference selections ? programmable speed/power ? output synchronization to timer1 clock input (comparator c2 only) 9.1 control registers both comparators have separate control and configu- ration registers: cm1con0 for c1 and cm2con0 for c2. in addition, comparator c2 has a second control register, cm2con1, for synchronization control and simultaneous reading of both comparator outputs. 9.1.1 comparator c1 control register the cm1con0 register (shown in register 9-1) contains the control and status bits for the following: ? comparator enable ? comparator input selection ? comparator reference selection ? output mode ? comparator speed setting c1on (cm1con0<7>) enables comparator c1 for operation. bits c1ch<1:0> of the cm1con0 register select the comparator input from the four analog pins an<7:5,1>. setting c1r of the cm1con0 register selects the c1v ref output of the comparator voltage reference module as the reference voltage for the comparator. clearing c1r selects the c1in+ input on the ra0/an0/ c1in+/icspdat pin. the output of the comparator is available internally via the c1out flag of the cm1con0 register. to make the output available for an external connection, the c1oe bit of the cm1con0 register must be set. the polarity of the comparator output can be inverted by setting the c1pol bit of the cm1con0 register. clearing c1pol results in a non-inverted output. a complete table showing the output state versus input conditions and the polarity bit is shown in table 9-1. table 9-1: c1 output state versus input conditions c1sp of the cm1con0 register configures the speed of the comparator. when c1sp is set, the comparator operates at its normal speed. clearing c1sp operates the comparator in a slower, low-power mode. note: to use an<7:5,1> as analog inputs the appropriate bits must be programmed to ? 1 ? in the ansel0 register. input condition c1pol c1out c1vn > c1vp 00 c1vn < c1vp 01 c1vn > c1vp 11 c1vn < c1vp 10 note 1: the internal output of the comparator is latched at the end of each instruction cycle. external outputs are not latched. 2: the c1 interrupt will operate correctly with c1oe set or cleared. 3: to output c1 on ra2/an2/t0cki/int/ c1out:(c1oe = 1 ) and (c1on = 1 ) and (trisa<2> = 0 ).
pic16f785/hv785 ds41249e-page 64 ? 2008 microchip technology inc. figure 9-1: comparator c1 si mplified block diagram note 1: when c1on = 0 , the c1 comparator will produce a ? 0 ? output to the xor gate. 2: output shown for reference only. for more detail, see figure 4-3. mux c1 c1pol c1out to pwm logic 0 1 2 3 c1on (1) c1sp c1ch<1:0> 2 0 1 c1r c1oe c1v ref mux rd_cm1con0 set c1if to c1vn c1vp ra2/an2/t0cki/int/c1out (2) ra1/an1/c12in0-/v ref /icspclk rc1/an5/c12in1-/ph1 rc2/an6/c12in2-/op2 rc3/an7/c12in3-/op1 ra0/an0/c1in+/icspdat dq en q1 data bus c1pol dq en cl q3*rd_cm1con0 nreset
? 2008 microchip technology inc. ds41249e-page 65 pic16f785/hv785 register 9-1: cm1con0: comparator c1 control register 0 r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 c1on c1out c1oe c1pol c1sp c1r c1ch1 c1ch0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 c1on: comparator c1 enable bit 1 = c1 comparator is enabled 0 = c1 comparator is disabled bit 6 c1out: comparator c1 output bit if c1pol = 1 (inverted polarity): c1out = 1 , c1vp < c1vn c1out = 0 , c1vp > c1vn if c1pol = 0 (non-inverted polarity): c1out = 1 , c1vp > c1vn c1out = 0 , c1vp < c1vn bit 5 c1oe: comparator c1 output enable bit 1 = c1out is present on the ra2/an2/t0cki/int/c1out pin (1) 0 = c1out is internal only bit 4 c1pol: comparator c1 output polarity select bit 1 = c1out logic is inverted 0 = c1out logic is not inverted bit 3 c1sp: comparator c1 speed select bit 1 = c1 operates in normal speed mode 0 = c1 operates in low-power, slow speed mode bit 2 c1r: comparator c1 reference select bit (non-inverting input) 1 = c1vp connects to c1v ref output 0 = c1vp connects to ra0/an0/c1in+/icspdat bit 1-0 c1ch<1:0>: comparator c1 channel select bits 00 = c1vn of c1 connects to ra1/an1/c12in0-/v ref /icspclk 01 = c1vn of c1 connects to rc1/an5/c12in1-/ph1 10 = c1vn of c1 connects to rc2/an6/c12in2-/op2 11 = c1vn of c1 connects to rc3/an7/c12in3-/op1 note 1: c1out will only drive ra2/an2/t0cki/int/c1out if: (c1oe = 1 ) and (c1on = 1 ) and (trisa<2> = 0 ).
pic16f785/hv785 ds41249e-page 66 ? 2008 microchip technology inc. 9.1.2 comparator c2 control registers the cm2con0 register is a functional copy of the cm1con0 register described in section 9.1.1 ?com- parator c1 control register? . a second control regis- ter, cm2con1, is also present for control of an additional synchronizing feature, as well as mirrors of both comparator outputs. 9.1.2.1 control register cm2con0 the cm2con0 register, shown in register 9-2, contains the control and status bits for comparator c2. setting c2on of the cm2con0 register enables comparator c2 for operation. bits c2ch<1:0> of the cm2con0 register select the comparator input from the four analog pins, an<7:5,1>. c2r of the cm2con0 register selects the reference to be used with the comparator. setting c2r of the cm2con0 register selects the c2v ref output of the comparator voltage reference module as the reference voltage for the comparator. clearing c2r selects the c2in+ input on the rc0/an4/c2in+ pin. the output of the comparator is available internally via the c2out bit of the cm2con0 register. to make the output available for an external connection, the c2oe bit of the cm2con0 register must be set. the comparator output, c2out, can be inverted by setting the c2pol bit of the cm2con0 register. clearing c2pol results in a non-inverted output. a complete table showing the output state versus input conditions and the polarity bit is shown in table 9-2. table 9-2: c2 output state versus input conditions c2sp of the cm2con0 register configures the speed of the comparator. when c2sp is set, the comparator operates at its normal speed. clearing c2sp operates the comparator in low-power mode. figure 9-2: comparator c2 simplified block diagram note: to use an<7:5,1> as analog inputs, the appropriate bits must be programmed to 1 in the ansel0 register. input condition c2pol c2out c2vn > c2vp 00 c2vn < c2vp 01 c2vn > c2vp 11 c2vn < c2vp 10 note 1: the internal output of the comparator is latched at the end of each instruction cycle. external outputs are not latched. 2: the c2 interrupt will operate correctly with c2oe set or cleared. an external output is not required for the c2 interrupt. 3: for c2 output on rc4/c2out/ph2: (c2oe = 1 ) and (c2on = 1 ) and (trisa<4> = 0 ). mux c2pol c2out to pwm logic 0 1 2 3 c2ch<1:0> 2 0 1 c2r from tmr1 clock note 1: when c2on = 0 , the c2 comparator will produce a ? 0 ? output to the xor gate. 2: timer1 gate control (see figure 6-1). 3: output shown for reference only. for more detail, see figure 4-13. c20e c2v ref mux dq en dq en cl dq rd_cm2con0 q3*rd_cm2con0 q1 set c2if to nreset c2vn c2vp rc4/c2out/ph2 (3) rc0/an4/c2in+ ra1/an1/c12in0-/v ref /icspclk rc1/an5/c12in1-/ph1 rc2/an6/c12in2-/op2 rc3/an7/c12in3-/op1 0 1 c2sync syncc2out (2) c2pol data bus mux c2 c2on (1) c2sp
? 2008 microchip technology inc. ds41249e-page 67 pic16f785/hv785 register 9-2: cm2con0: comparator c2 control register 0 r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 c2on c2out c2oe c2pol c2sp c2r c2ch1 c2ch0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 c2on: comparator c2 enable bit 1 = c2 comparator is enabled 0 = c2 comparator is disabled bit 6 c2out: comparator c2 output bit if c2pol = 1 (inverted polarity): c2out = 1 , c2vp < c2vn c2out = 0 , c2vp > c2vn if c2pol = 0 (non-inverted polarity): c2out = 1 , c2vp > c2vn c2out = 0 , c2vp < c2vn bit 5 c2oe: comparator c2 output enable bit 1 = c2out is present on rc4/c2out/ph2 (1) 0 = c2out is internal only bit 4 c2pol: comparator c2 output polarity select bit 1 = c2out logic is inverted 0 = c2out logic is not inverted bit 3 c2sp: comparator c2 speed select bit 1 = c2 operates in normal speed mode 0 = c2 operates in low power, slow speed mode. bit 2 c2r: comparator c2 reference select bits (non-inverting input) 1 = c2vp connects to c2v ref 0 = c2vp connects to rc0/an4/c2in+ bit 1-0 c2ch<1:0>: comparator c2 channel select bits 00 = c2vn of c2 connects to ra1/an1/c12in0-/v ref /icspclk 01 = c2vn of c2 connects to rc1/an5/c12in1-/ph1 10 = c2vn of c2 connects to rc2/an6/c12in2-/op2 11 = c2vn of c2 connects to rc3/an7/c12in3-/op1 note 1: c2out will only drive rc4/c2out/ph2 if: (c2oe = 1 ) and (c2on = 1 ) and (trisc<4> = 0 ).
pic16f785/hv785 ds41249e-page 68 ? 2008 microchip technology inc. 9.1.2.2 control register cm2con1 comparator c2 has one additional feature: its output can be synchronized to the timer1 clock input. setting c2sync of the cm2con1 register synchronizes the output of comparator 2 to the falling edge of the timer1 clock input (see figure 9-2 and register 9-3). the cm2con1 register also contains mirror copies of both comparator outputs, mc1out and mc2out of the cm2con1 register. the ability to read both out- puts simultaneously from a single register eliminates the timing skew of reading separate registers. register 9-3: cm2con1: comparator c2 control register 1 note: obtaining the status of c1out or c2out by reading cm2con1 does not affect the comparator interrupt mismatch registers. r-0 r-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 mc1out mc2out ? ? ? ? t1gss c2sync bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 mc1out : mirror copy of c1out bit (cm1con0<6>) bit 6 mc2out : mirror copy of c2out bit (cm2con0<6>) bit 5-2 unimplemented: read as ? 0 ? bit 1 t1gss : timer1 gate source select bit 1 = timer1 gate source is ra4/an3/t1g/osc2/clkout 0 = timer1 gate source is syncc2out. bit 0 c2sync : c2 output synchronous mode bit 1 = c2 output is synchronous to falling edge of tmr1 clock 0 = c2 output is asynchronous
? 2008 microchip technology inc. ds41249e-page 69 pic16f785/hv785 9.2 comparator outputs the comparator outputs are read through the cm1con0, com2con0 or cm2con1 registers. cm1con0 and cm2con0 each contain the individual comparator output of comparator 1 and comparator 2, respectively. cm2con2 contains a mirror copy of both comparator outputs facilitating a simultaneous read of both comparators. these bits are read-only. the comparator outputs may also be directly output to the ra2/an2/t0cki/int/c1out and rc4/c2out/ph2 i/o pins. when enabled, multiplexers in the output path of the ra2 and rc4 pins will switch and the output of each pin will be the unsynchronized output of the com- parator. the uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. figure 9-1 and figure 9-2 show the output block diagrams for comparators 1 and 2, respectively. the tris bits will still function as an output enable/ disable for the ra2/an2/t0cki/int/c1out and rc4/ c2out/ph2 pins while in this mode. the polarity of the comparator outputs can be changed using the c1pol and c2pol bits of the cmxcon0 register. timer1 gate source can be configured to use the t1g pin or comparator 2 output as selected by the t1gss bit of the cm2con1 register. the timer1 gate feature can be used to time the duration or interval of analog events. the output of comparator 2 can also be syn- chronized with timer1 by setting the c2sync bit of the cm2con1 register. when enabled, the output of comparator 2 is latched on the falling edge of the timer1 clock source. if a prescaler is used with timer1, comparator 2 is latched after the prescaler. to prevent a race condition, the comparator 2 output is latched on the falling edge of the timer1 clock source and timer1 increments on the rising edge of its clock source. see the comparator 2 block diagram (figure 9-2) and the timer1 block diagram (figure 6-1) for more information. it is recommended to synchronize comparator 2 with timer1 by setting the c2sync bit when comparator 2 is used as the timer1 gate source. this ensures timer1 does not miss an increment if comparator 2 changes during an increment. 9.3 comparator interrupts the comparator interrupt flags are set whenever there is a change in the output value of its respective compar- ator. software will need to maintain information about the status of the output bits, as read from cm2con0<7:6>, to determine the actual change that has occurred. the cxif bits, pir1<4:3>, are the comparator interrupt flags. each comparator interrupt bit must be reset in software by clearing it to ? 0 ?. since it is also possible to write a ? 1 ? to this register, a simulated interrupt may be initiated. the cxie bits of the pie1 register and the peie bit of the intcon register must be set to enable the inter- rupts. in addition, the gie bit must also be set. if any of these bits are cleared, the interrupt is not enabled, though the cxif bits will still be set if an interrupt con- dition occurs. the comparator interrupt of the pic16f785/hv785 differs from previous designs in that the interrupt flag is set by the mismatch edge and not the mismatch level. this means that the interrupt flag can be reset without the additional step of reading or writing the cmxcon0 register to clear the mismatch registers. when the mismatch registers are not cleared, an interrupt will not occur when the comparator output returns to the previous state. when the mismatch registers are cleared, an interrupt will occur when the comparator returns to the previous state. 9.4 effects of reset a reset forces all registers to their reset state. this disables both comparators. note 1: if a change in the cmxcon0 register (cxout) should occur when a read operation is being executed (start of the q2 cycle), then the cxif of the pir1 reg- ister interrupt flag may not get set. 2: when either comparator is first enabled, bias circuitry in the comparator module may cause an invalid output from the comparator until the bias circuitry is sta- ble. allow about 1 s for bias settling then clear the mismatch condition and inter- rupt flags before enabling comparator interrupts.
pic16f785/hv785 ds41249e-page 70 ? 2008 microchip technology inc. 10.0 voltage references there are two voltage references available in the pic16f785/hv785: the voltage referred to as the comparator reference (cv ref ) is a variable voltage based on v dd ; the voltage referred to as the vr refer- ence (vr) is a fixed voltage derived from a stable band gap source. each source may be individually routed internally to the comparators or output, buffered or unbuffered, on the ra1/an1/c12in0-/v ref /icspclk pin. 10.1 comparator reference the comparator module also allows the selection of an internally generated voltage reference for one of the comparator inputs. the vrcon register (register 10-1) controls the voltage reference module shown in figure 10-1. 10.1.1 configuring the voltage reference the voltage reference can output 32 distinct voltage levels, 16 in a high range and 16 in a low range. the following equation determines the output voltages: equation 10-1: cv ref output voltage 10.1.2 voltage reference accuracy/error the full range of v ss to v dd cannot be realized due to the construction of the module. the transistors on the top and bottom of the resistor ladder network (figure 10-1) keep cv ref from approaching v ss or v dd . the exception is when the module is disabled by clearing all cvroe, c1vren and c2vren bits. when disabled with vr<3:0> = 0000 and vrr = 1 the refer- ence voltage will be v ss . this allows the comparators to detect a zero-crossing and not consume cv ref module current. the voltage reference is v dd derived and therefore, the cv ref output changes with fluctuations in v dd . the tested absolute accuracy of the comparator voltage reference can be found in table 19-8. v rr = 1 (low range): cv ref = vr<3:0> x v dd /24 v rr = 0 (high range): cv ref = (v dd /4) + (vr<3:0> x v dd /32)
? 2008 microchip technology inc. ds41249e-page 71 pic16f785/hv785 figure 10-1: comparator volt age reference block diagram vrr 8r vr3:vr0 16-1 analog 8rrr rr c1v ref to 16 stages comparator 1 input cvren (1) v dd mux 0 1 c2v ref to comparator 2 input 0 1 vr 1.2 v c2vren c1vren cv ref cvroe note 1: see register 10-1, bits 3-0. 15 0
pic16f785/hv785 ds41249e-page 72 ? 2008 microchip technology inc. register 10-1: vrcon: voltage reference control register r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 c1vren (1) c2vren (1) vrr ?vr3vr2vr1vr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 c1vren : comparator 1 voltage reference enable bit (1) 1 = cv ref circuit powered on and routed to c1v ref input of comparator 1 0 = 1.2 volt vr routed to c1v ref input of comparator 1 bit 6 c2vren : comparator 2 voltage reference enable bit (1) 1 = cv ref circuit powered on and routed to c2v ref input of comparator 2 0 = 1.2 volt vr routed to c2v ref input of comparator 2 bit 5 vrr : comparator voltage reference cv ref range selection bit 1 = low range 0 = high range bit 4 unimplemented : read as ? 0 ? bit 3-0 vr<3:0> : comparator voltage reference cv ref value selection 0 vr<3:0> 15 when vrr = 1 and cvren = 1 : cv ref = (vr<3:0> x v dd /24) when vrr = 0 and cvren = 1 : cv ref = (v dd /4) + (vr<3:0> x v dd /32) when cxvren = 0 and vren = 1 : cxv ref = 1.2v from vr module note 1: when c1vren, c2vren and cvroe (register 10-2) are all low, the cv ref circuit is powered down and does not contribute to i dd current.
? 2008 microchip technology inc. ds41249e-page 73 pic16f785/hv785 10.2 vr reference module the vr reference module generates a 1.2v nominal output voltage for use by the adc and comparators. the output voltage can also be brought out to the v ref pin for user applications. this module uses a bandgap as a reference. see table 19-9 for detailed specifica- tions. register 10-2 shows the control register for the vr module. register 10-2: refcon: voltage reference control register u-0 u-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 ? ? bgst vrbb vren vroe cvroe ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5 bgst: band gap reference voltage stable flag bit 1 = reference is stable 0 = reference is not stable bit 4 vrbb: voltage reference buffer bypass bit 1 = v ref output is not buffered. power is removed from buffer amplifier. 0 = v ref output is buffered (1) bit 3 vren: voltage reference enable bit (vr = 1.2v nominal) (2) 1 = vr reference is enabled 0 = vr reference is disabled and does not consume any current bit 2 vroe: voltage reference output enable bit if cvroe = 0 : 1 = v ref output on ra1/an1/c12in0-/v ref /icspclk pin is 1.2 volt vr analog reference 0 = disabled, 1.2 volt vr analog reference is used internally only if cvroe = 1 : vroe has no effect. bit 1 cvroe : comparator voltage reference output enable bit (see figure 10-2) 1 = v ref output on ra1/an1/c12in0-/v ref /icspclk pin is cv ref voltage 0 = v ref output on ra1/an1/c12in0-/v ref /icspclk pin is controlled by vroe bit 0 unimplemented: read as ? 0 ? note 1: buffer amplifier common mode limitations require v ref (v dd - 1.4)v for buffered output. 2: vren is fixed high for pic16hv785 device.
pic16f785/hv785 ds41249e-page 74 ? 2008 microchip technology inc. 10.2.1 vr stabilization period when the voltage reference module is enabled, it will require some time for the reference and its amplifier circuits to stabilize. the user program must include a small delay routine to allow the module to settle. see section 19.0 ?electrical specifications? for the minimum delay requirement. figure 10-2: vr reference block diagram table 10-1: registers associated with comparator and voltage reference modules name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets ansel0 ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 1111 1111 1111 1111 cm1con0 c1on c1out c1oe c1pol c1sp c1r c1ch1 c1ch0 0000 0000 0000 0000 cm2con0 c2on c2out c2oe c2pol c2sp c2r c2ch1 c2ch0 0000 0000 0000 0000 cm2con1 mc1out mc2out ? ? ? ? t1gss c2sync 00-- --10 00-- --10 pie1 eeie adie ccp1ie c2ie c1ie osfie tmr2ie tmr1ie 0000 ---0 0000 ---0 pir1 eeif adif ccp1if c2if c1if osfif tmr2if tmr1if 0000 ---0 0000 ---0 porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --xx xxxx --uu uuuu portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu refcon ? ? bgst vrbb vren vroe cvroe ? --00 000- --00 000- trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 vrcon c1vren c2vren vrr ? vr3 vr2 vr1 vr0 000- 0000 000- 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used for comparator. ra1/an1/c12in0-/v ref vren voltage reference en rdy to c v ref mux bgst vr 1 0 1x analog buffer cv ref vrbb (1) vr out cvroe (cvroe + (vren*vroe)) 1 0 vr in note 1: buffered output requires vr in = (v dd - 1.4)v. 2: vren is fixed high for pic16hv785 device.
? 2008 microchip technology inc. ds41249e-page 75 pic16f785/hv785 11.0 operational amplifier (opa) module the opa module has the following features: ? two independent operational amplifiers ? external connections to all ports ? 3 mhz gain bandwidth product (gbwp) 11.1 control registers the opa1con register, shown in register 11-1, controls opa1. opa2con, shown in register 11-2, controls opa2. 11.2 opaxcon register the opa module is enabled by setting the opaon bit of the opaxcon register. when enabled, opaon forces the output driver of rc3/an7/c12in3-/op1 for opa1, and rc2/an6/c12in2-/op2 for opa2, into tristate to prevent contention between the driver and the opa output. the adc and comparator inputs which share the op amp pins operate normally when the op amp is enabled. figure 11-1: opa module block diagram note: when opa1 or opa2 is enabled, the rc3/an7/c12in3-/op1 pin, or rc2/an6/c12in2-/op2 pin, respectively, is driven by the op amp output, not by the portc driver. refer to table 19-11 for the electrical specifications for the op amp output drive capability. opa1 opa1con to adc and comparator muxs rc7/an9/op1+ rc6/an8/op1- rc3/an7/c12in3-/op1 opa2 opa2con to adc and comparator muxs rb5/an11/op2+ rb4/an10/op2- rc2/an6/c12in2-/op2
pic16f785/hv785 ds41249e-page 76 ? 2008 microchip technology inc. register 11-1: opa1con: op amp 1 control register register 11-2: opa2con: op amp 2 control register r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 opaon ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 opaon: op amp enable bit 1 = op amp 1 is enabled 0 = op amp 1 is disabled bit 6-0 unimplemented: read as ? 0 ? r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 opaon ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 opaon: op amp enable bit 1 = op amp 2 is enabled 0 = op amp 2 is disabled bit 6-0 unimplemented: read as ? 0 ?
? 2008 microchip technology inc. ds41249e-page 77 pic16f785/hv785 11.3 effects of a reset a device reset forces all registers to their reset state. this disables both op amps. 11.4 opa module performance common ac and dc performance specifications for the opa module: ? common mode voltage range ? leakage current ? input offset voltage ? open loop gain ? gain bandwidth product (gbwp) common mode voltage range is the specified voltage range for the opa+ and opa- inputs, for which the opa module will perform to within its specifications. the opa module is designed to operate with input voltages between 0 and v dd -1.4v. behavior for common mode voltages greater than v dd -1.4v, or below 0v, are beyond the normal operating range. leakage current is a measure of the small source or sink currents on the opa+ and opa- inputs. to mini- mize the effect of leakage currents, the effective imped- ances connected to the opa+ and opa- inputs should be kept as small as possible and equal. input offset voltage is a measure of the voltage differ- ence between the opa+ and opa- inputs in a closed loop circuit with the opa in its linear region. the offset voltage will appear as a dc offset in the output equal to the input offset voltage, multiplied by the gain of the circuit. the input offset voltage is also affected by the common mode voltage. open loop gain is the ratio of the output voltage to the differential input voltage, (opa+) - (opa-). the gain is greatest at dc and falls off with frequency. gain bandwidth product or gbwp is the frequency at which the open loop gain falls off to 0 db. 11.5 effects of sleep when enabled, the op amps continue to operate and consume current while the processor is in sleep mode. table 11-1: registers associated with the opa module name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets ansel0 ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 1111 1111 1111 1111 ansel1 ? ? ? ? ans11 ans10 ans9 ans8 ---- 1111 ---- 1111 opa1con opaon ? ? ? ? ? ? ? 0--- ---- 0--- ---- opa2con opaon ? ? ? ? ? ? ? 0--- ---- 0--- ---- trisb trisb7 trisb6 trisb5 trisb4 ? ? ? ? 1111 ---- 1111 ---- trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used for the opa module.
pic16f785/hv785 ds41249e-page 78 ? 2008 microchip technology inc. notes:
? 2008 microchip technology inc. ds41249e-page 79 pic16f785/hv785 12.0 analog-to-digital converter (a/d) module the analog-to-digital converter (a/d) allows conversion of an analog input signal to a 10-bit binary representa- tion of that signal. the pic16f785/hv785 has twelve analog i/o inputs, plus two internal inputs, multiplexed into one sample and hold circuit. the output of the sam- ple and hold is connected to the input of the converter. the converter generates a binary result via successive approximation and stores the result in a 10-bit register. the voltage reference used in the conversion is soft- ware selectable to either v dd or a voltage applied by the v ref pin. figure 12-1 shows the block diagram of the a/d on the pic16f785/hv785. figure 12-1: a/d block diagram a/d v dd v ref adon (1) go/done vcfg = 1 vcfg = 0 chs<3:0> adresh adresl 10 10 adfm v ss ra0/an0/c1in+/icspdat ra1/an1/c12in0-/v ref /icspclk ra2/an2/t0cki/int/c1out ra4/an3/t1g/osc2/clkout rc0/an4/c2in+ rc1/an5/c12in1-/ph1 rc2/an6/c12in2-/op2 rc3/an7/c12in3-/op1 rc6/an8/op1- rc7/an9/op1+ rb4/an10/op2- rb5/an11/op2+ cv ref vr 0 13 note 1: when adon = 0 all input channels are disconnected from adc (no loading).
pic16f785/hv785 ds41249e-page 80 ? 2008 microchip technology inc. 12.1 a/d configuration and operation there are four registers available to control the functionality of the a/d module: 1. ansel0 (register 12-1) 2. ansel1 (register 12-2) 3. adcon0 (register 12-3) 4. adcon1 (register 12-4) 12.1.1 analog port pins the ans<11:0> bits, of the ansel1 and ansel0 registers, and the trisa<4,2:0>, trisb<5:4> and trisc<7:6,3:0>> bits control the operation of the a/d port pins. set the corresponding trisx bits to ? 1 ? to set the pin output driver to its high-impedance state. like- wise, set the corresponding ansx bit to disable the dig- ital input buffer. 12.1.2 channel selection there are fourteen analog channels on the pic16f785/ hv785. the chs<3:0> bits of the adcon0 register control which channel is connected to the sample and hold circuit. 12.1.3 voltage reference there are two options for the voltage reference to the a/d converter: either v dd is used or an analog voltage applied to v ref is used. the vcfg bit of the adcon0 register controls the voltage reference selection. if vcfg is set, then the voltage on the v ref pin is the ref- erence; otherwise, v dd is the reference. 12.1.4 conversion clock the a/d conversion cycle requires 11 t ad . the source of the conversion clock is software selectable via the adcs bits of the adcon1 register. there are seven possible clock options: ?f osc /2 ?f osc /4 ?f osc /8 ?f osc /16 ?f osc /32 ?f osc /64 ?f rc (dedicated internal oscillator) for correct conversion, the a/d conversion clock (1/t ad ) must be selected to ensure a minimum t ad of 1.6 s. table 12-1 shows a few t ad calculations for selected frequencies. table 12-1: t ad vs. device operating frequencies note: analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. a/d clock source (t ad ) device frequency operation adcs2:adcs0 20 mhz 5 mhz 4 mhz 1.25 mhz 2 t osc 000 100 ns (2) 400 ns (2) 500 ns (2) 1.6 s 4 t osc 100 200 ns (2) 800 ns (2) 1.0 s (2) 3.2 s 8 t osc 001 400 ns (2) 1.6 s2.0 s6.4 s 16 t osc 101 800 ns (2) 3.2 s4.0 s 12.8 s (3) 32 t osc 010 1.6 s6.4 s 8.0 s (3) 25.6 s (3) 64 t osc 110 3.2 s 12.8 s (3) 16.0 s (3) 51.2 s (3) a/d rc x11 2-6 s (1), (4) 2-6 s (1), (4) 2-6 s (1), (4) 2-6 s (1), (4) legend: shaded cells are outside of recommended range. note 1: the a/d rc source has a typical t ad time of 4 s for v dd > 3.0v. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: when the device frequency is greater than 1 mhz, the a/d rc clock source is only recommended if the conversion will be performed during sleep.
? 2008 microchip technology inc. ds41249e-page 81 pic16f785/hv785 12.1.5 starting a conversion the a/d conversion is initiated by setting the go/done bit (adcon0<1>). when the conversion is complete, the a/d module: ? clears the go/done bit ? sets the adif flag (pir1<6>) ? generates an interrupt (if enabled) if the conversion must be aborted, the go/done bit can be cleared in software. the adresh:adresl registers will not be updated with the partially complete a/d conversion sample. instead, the adresh:adresl registers will retain the value of the previous conversion. after an aborted conversion, a 2t ad delay is required before another acquisition can be initiated. following the delay, an input acquisition is automatically started on the selected channel. figure 12-2: a/d conversion t ad cycles 12.1.6 conversion output the a/d conversion can be supplied in two formats: left or right justified. the adfm bit of the adcon0 register controls the output format. figure 12-3 shows the out- put formats. figure 12-3: 10-bit a/d result format note: the go/done bit should not be set in the same instruction that turns on the a/d. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 9 set go bit holding capacitor is disconnected fr om analog input (typically 100 ns) b9 b8 b7 b6 b5 b4 b3 b2 t ad 10 t ad 11 b1 b0 t cy to t ad conversion starts adresh and adresl registers are loaded, go bit is cleared, adif bit is set, holding capacitor is connected to analog input adresh (address:1eh) adresl (address:9eh) (adfm = 0 )msb lsb bit 7bit 0bit 7bit 0 10-bit a/d result unimplemented: read as ? 0 ? (adfm = 1 ) msb lsb bit 7bit 0bit 7bit 0 unimplemented: read as ? 0 ? 10-bit a/d result
pic16f785/hv785 ds41249e-page 82 ? 2008 microchip technology inc. register 12-1: ansel0: analog select register register 12-2: ansel1: analog select register table 12-2: analog select cross reference r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 ans<7:0> : analog select bits analog select between analog or digital function on pins an<7:0>, respectively. 1 = analog input. pin is assigned as analog input. (1) 0 = digital i/o. pin is assigned to port or special function. note 1: setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and inter- rupt-on-change, if available. the corresponding tris bit must be set to input mode in order to allow exter- nal control of the voltage on the pin. port reads of pins configured assigned as analog inputs will read as ? 0 ?. u-0 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ? ans11 ans10 ans9 ans8 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 unimplemented: read as ? 0 ? bit 3-0 ans<11:8> : analog select bits analog select between analog or digital function on pins an<11:8>, respectively. 1 = analog input. pin is assigned as analog input. (1) 0 = digital i/o. pin is assigned to port or special function. note 1: setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and inter- rupt-on-change, if available. the corresponding tris bit must be set to input mode in order to allow exter- nal control of the voltage on the pin. port reads of pins assigned as analog inputs will read as ? 0 ?. mode reference analog select ans11 ans10 ans9 ans8 ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 analog channel an11an10an9an8an7an6an5an4an3an2an1an0 i/o pin rb5 rb4 rc7 rc6 rc3 rc2 rc1 rc0 ra4 ra2 ra1 ra0
? 2008 microchip technology inc. ds41249e-page 83 pic16f785/hv785 register 12-3: adcon0: a/d control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adfm vcfg chs3 chs2 chs1 chs0 go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 adfm: a/d result formed select bit 1 = right justified 0 = left justified bit 6 vcfg : voltage reference bit 1 = v ref pin 0 = v dd bit 5-2 chs<3:0>: analog channel select bits 0000 = channel 00 (an0) 0001 = channel 01 (an1) 0010 = channel 02 (an2) 0011 = channel 03 (an3) 0100 = channel 04 (an4) 0101 = channel 05 (an5) 0110 = channel 06 (an6) 0111 = channel 07 (an7) 1000 = channel 08 (an8) 1001 = channel 09 (an9) 1010 = channel 10 (an10) 1011 = channel 11 (an11) 1100 =cv ref 1101 =vr 1110 = reserved. do not use. 1111 = reserved. do not use. bit 1 go/done : a/d conversion status bit 1 = a/d conversion cycle in progress. setting this bit starts an a/d conversion cycle. this bit is automatically cleared by hardware when the a/d conversion has completed. 0 = a/d conversion completed/not in progress bit 0 adon: a/d enable bit 1 = a/d converter module is enabled 0 = a/d converter is shut-off and consumes no operating current
pic16f785/hv785 ds41249e-page 84 ? 2008 microchip technology inc. register 12-4: adcon1: a/ d control register 1 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? adcs2 adcs1 adcs0 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6-4 adcs<2:0>: a/d conversion clock select bits 000 =f osc /2 001 =f osc /8 010 =f osc /32 x11 =f rc (clock derived from a dedicated internal oscillator = 500 khz max) 100 =f osc /4 101 =f osc /16 110 =f osc /64 bit 3-0 unimplemented: read as ? 0 ?
? 2008 microchip technology inc. ds41249e-page 85 pic16f785/hv785 12.1.7 configuring the a/d after the a/d module has been configured as desired, the selected channel must be acquired before the conversion is started. the analog input channels must have their corresponding tris bits selected as inputs. to determine sample time, see table 19-16 and table 19-17. after this sample time has elapsed, the a/d conversion can be started. these steps should be followed for an a/d conversion: 1. configure the a/d module: ? configure analog/digital i/o (ansx) ? select a/d conversion clock in the adcon1 register ? configure voltage reference in the adcon0 register ? select a/d input channel in the adcon0 register ? select result format in the adcon0 register ? turn on a/d module in the adcon0 register 2. configure a/d interrupt (if desired): ? clear adif bit of the pir1 register ? set adie bit of the pie1 register ? set peie and gie bits of the intcon regis- ter 3. wait the required acquisition time. 4. start conversion: ? set go/done bit (adcon0<1>) 5. wait for a/d conversion to complete, by either: ? polling for the go/done bit to be cleared (with interrupts disabled); or ? waiting for the a/d interrupt 6. read a/d result register pair (adresh:adresl), clear bit adif if required. 7. for next conversion, go to step 1 or step 2 as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2 t ad is required before the next acquisition starts. example 12-1: a/d conversion ;this code block configures the a/d ;for polling, vdd reference, r/c clock ;and ra0 input. ; ;conversion start and wait for complete ;polling code included. ; bcf status,rp1 ;bank 1 bsf status,rp0 ; movlw b?01110000? ;a/d rc clock movwf adcon1 bsf trisa,0 ;set ra0 to input bsf ansel0,0 ;set ra0 to analog bcf status,rp0 ;bank 0 movlw b?10000001? ;right, vdd vref, an0 movwf adcon0 call sampletime ;wait min sample time bsf adcon0,go ;start conversion btfsc adcon0,go ;is conversion done? goto $-1 ;no, test again movf adresh,w ;read upper 2 bits movwf resulthi bsf status,rp0 ;bank 1 movf adresl,w ;read lower 8 bits bcf status,rp0 ;bank 0 movwf resultlo
pic16f785/hv785 ds41249e-page 86 ? 2008 microchip technology inc. 12.2 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 12-4. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), see figure 12-4. the maximum recom- mended impedance for analog sources is 10 k . as the impedance is decreased, the acquisition time may be decreased. after the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 12-1 may be used. this equation assumes that 1/2 lsb error is used (1024 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. equation 12-1: acquisition time example note 1: the reference voltage (v ref ) has no effect on the equation, since it cancels itself out. 2: the charge holding capacitor (c hold ) is not discharged after each conversion. 3: the maximum recommended impedance for analog sources is 10 k . this is required to meet the pin leakage specification. t acq amplifier settling time hold capacitor charging time temperature coefficient ++ = t amp tc t coff ++ = 5s tc temperature - 25c () 0.05s/c () [] ++ = t cc hold ric rss rs ++ () ln(1/2047) ? = 10pf 1k 7k 10k ++ () ? ln(0.0004885) = 1.37 = s tacq 5s 1.37s 50c- 25c () 0.05s/c () [] ++ = 7.62 s = v applied 1e tc ? rc --------- ? ?? ?? ?? v applied 1 1 2047 ----------- - ? ?? ?? = v applied 1 1 2047 ----------- - ? ?? ?? v chold = v applied 1e t c ? rc --------- - ? ?? ?? ?? v chold = ;[1] vchold charged to within 1/2 lsb ;[2] vchold charge response to vapplied ;combining [1] and [2] the value for tc can be approximated with the following equations: solving for tc: therefore: temperature 50c and external impedance of 10k 5.0v v dd = assumptions:
? 2008 microchip technology inc. ds41249e-page 87 pic16f785/hv785 figure 12-4: analog input model r ss c pin va r s anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss c hold = dac capacitance v ss 6v sampling switch 5v 4v 3v 2v 567891011 (k ) v dd = 10 pf 500 na r ss legend: c pin = input capacitance v t = threshold voltage i leakage = leakage current at the pin due to various junctions r ic = interconnect resistance ss = sampling switch c hold = sample/hold capacitance (from dac)
pic16f785/hv785 ds41249e-page 88 ? 2008 microchip technology inc. 12.3 a/d operation during sleep the a/d converter module can operate during sleep. this requires the a/d clock source to be set to the f rc option. when the rc clock source is selected, the a/d waits one instruction before starting the conversion. this allows the sleep instruction to be executed, thus eliminating much of the switching noise from the con- version. when the conversion is complete, the go/ done bit is cleared and the result is loaded into the adresh:adresl registers. if the a/d interrupt is enabled (adie and peie bits set), the device awakens from sleep. if the gie bit of the intcon register is set, the program counter is set to the interrupt vector (0004h). if gie is clear, the next instruction is executed. if the a/d interrupt is not enabled, the a/d module is turned off, although the adon bit remains set. when the a/d clock source is something other than rc, a sleep instruction causes the present conversion to be aborted and the a/d module is turned off. the adon bit remains set. figure 12-5: a/d transfer function 3ffh 3feh a/d output code 3fdh 3fch 004h 003h 002h 001h 000h full-scale 3fbh 1 lsb ideal 0v zero-scale transition v ref transition 1 lsb ideal full-scale range analog input voltage
? 2008 microchip technology inc. ds41249e-page 89 pic16f785/hv785 12.4 effects of reset a device reset forces all registers to their reset state. thus, the a/d module is turned off and any pending conversion is aborted. the adresh:adresl registers are unchanged. 12.5 use of the ccp trigger an a/d conversion can be started by the ?special event trigger? of the ccp module. this requires that the ccp1m3:ccp1m0 bits of the ccp1con register be programmed as ? 1011 ? and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/done bit will be set, starting the a/d conversion and the timer1 counter will be reset to zero. timer1 is reset to automatically repeat the a/d acquisition period with minimal software overhead (moving the adresh:adresl to the desired location). the appropriate analog input channel must be selected and the minimum acquisition done before the ?special event trigger? sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), then the ?special event trigger? will be ignored by the a/d module, but will still reset the timer1 counter. see section 8.0 ?capture/compare/pwm (ccp) module? for more information. table 12-3: summary of a/d registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets adcon0 adfm vcfg chs3 chs2 chs1 chs0 go/done adon 0000 0000 0000 0000 adcon1 ? adcs2 adcs1 adcs0 ? ? ? ? -000 ---- -000 ---- adresh most significant 8 bits of the left justified a/d result or 2 bits of the right justified result xxxx xxxx uuuu uuuu adresl least significant 2 bits of the left justified a/d result or 8 bits of the right justified result xxxx xxxx uuuu uuuu ansel0 ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 1111 1111 1111 1111 ansel1 ? ? ? ? ans11 ans10 ans9 ans8 ---- 1111 ---- 1111 intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 pie1 eeie adie ccp1ie c2ie c1ie osfie tmr2ie tmr1ie 0000 0000 0000 0000 pir1 eeif adif ccp1if c2if c1if osfif tmr2if tmr1if 0000 0000 0000 0000 porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --xx xxxx --uu uuuu portb rb7 rb6 rb5 rb4 ? ? ? ? xxxx ---- uuuu ---- portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 trisb trisb7 trisb6 trisb5 trisb4 ? ? ? ? 1111 ---- 1111 ---- trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, ? = unimplemented read as ? 0 ?. shaded cells are not used for a/d module.
pic16f785/hv785 ds41249e-page 90 ? 2008 microchip technology inc. notes:
? 2008 microchip technology inc. ds41249e-page 91 pic16f785/hv785 13.0 two-phase pwm the two-phase pwm (pulse width modulator) is a stand-alone peripheral that supports: ? single or dual-phase pwm ? single complementary output pwm with overlap/ delay ? sync input/output to cascade devices for additional phases setting either, or both, of the ph1en or ph2en bits of the pwmcon0 register will activate the pwm module (see register 13-1). if ph1 is used then trisc<1> must be cleared to configure the pin as an output. the same is true for trisc<4> when using ph2. both ph1en and ph2en must be set when using complementary mode. 13.1 pwm period the pwm period is derived from the main clock (f osc ), the pwm prescaler and the period counter (see figure 13-1). the prescale bits of the pwmp register, (see register 13-2) determine the value of the clock divider which divides the system clock (f osc ) to the pwm_clk. this pwm_clk is used to drive the pwm counter. in master mode, the pwm counter is reset when the count reaches the period count of the per register, (see register 13-2), which determines the frequency of the pwm. the relationship between the pwm frequency, prescale and period count is shown in equation 13-1. equation 13-1: pwm frequency the maximum pwm frequency is f osc /2, since the period count must be greater than zero. in slave mode, the period counter is reset by the sync input, which is the master device period counter reset. for proper operation, the slave period count should be equal to or greater than that of the master. 13.2 pwm phase each enabled phase output is driven active when the phase counter matches the corresponding pwm phase count in the ph register (see register 13-3 and register 13-4). the phase output remains true until ter- minated by a feedback signal from either of the com- parators or the auto-shutdown activates. phase granularity is a function of the period count value. for example, if per<4:0> = 3, each output can be shifted in 90 steps (see equation 13-2) . equation 13-2: phase resolution 13.3 pwm duty cycle each pwm output is driven inactive, terminating the drive period, by asynchronous feedback through the internal comparators. the duty cycle resolution is in effect infinitely adjustable. either or both comparators can be used to reset the pwm by setting the corre- sponding comparator enable bit (cxen, see register 13-3). duty cycles of 100% can be obtained by suppressing the feedback which would otherwise terminate the pulse. the comparator outputs can be ?held off?, or blanked, by enabling the corresponding blank bit (blankx, see register 13-1) for each phase. the blank bit disables the comparator outputs for 1/2 of a system clock (f osc ), thus ensuring at least t osc /2 active time for the pwm output. blanking avoids early termination of the pwm output which may result due to switching transients at the beginning of the cycle. 13.4 master/slave operation multiple chips can operate together to achieve addi- tional phases by operating one as the master and the others as slaves. when the pwm is configured as a master, the rb7/sync pin is an output and generates a high output for one pwm_clk period at the end of each pwm period (see figure 13-4). when the pwm is configured as a slave, the rb7/ sync pin is an input. the high input from a master in this configuration resets the pwm period counter which synchronizes the slave unit at the end of each pwm period. proper operation of a slave device requires a common external f osc clock source to drive the mas- ter and slave. the pwm prescale value of the slave device must also be identical to that of the master. as mentioned previously, the slave period count value must be greater than or equal to that of the master. the pwm counter will be reset and held at zero when both ph1en and ph2en of the pwmcon0 register are false. if the pwm is configured as a slave, the pwm counter will remain reset at zero until the first sync input is received. pwm freq = f osc (2 pwmp ? (per + 1) phase deg = (per + 1) 360
pic16f785/hv785 ds41249e-page 92 ? 2008 microchip technology inc. 13.5 active pwm output level the pwm output signal can be made active-high or active-low by setting or resetting the corresponding pol bit (see register 13-3 and register 13-4). when pol is ? 1 ? the active output state is v ol . when pol is ? 0 ? the active output state is v oh . 13.6 auto-shutdown and auto-restart when the pwm is enabled, the pwm outputs may be configured for auto-shutdown by setting the pasen bit (see register 13-1). v il on the ra2/an2/t0cki/int/ c1out pin will cause a shutdown event if auto-shut- down is enabled. an auto-shutdown event immediately places the pwm outputs in the inactive state (see section 13.5 ?active pwm output level? ) and the pwm phase and period counters are reset and held to zero. the pwmase bit (see register 13-2) is set by hard- ware when a shutdown event occurs. if automatic restarts are not enabled (prsen = 0 , see register 13-1), pwm operation will not resume until the pwmase bit is cleared by firmware after the shutdown condition clears. the pwmase bit can not be cleared as long as the shutdown condition exists. if automatic restarts are not enabled, the auto-shutdown mode can be forced by writing a ? 1 ? to the pwmase bit. if automatic restarts are enabled (prsen = 1 ), the pwmase bit is automatically cleared and pwm operation resumes when the auto-shutdown event clears (v ih on the ra2/an2/t0cki/int/c1out pin). figure 13-1: two-phase pwm simplified block diagram prescale pwmph1 pwmph1 pwmph1 pwmph1<4:0> phase counter f osc c1out c2out pwmp<1:0> per<4:0> pwm_clk 5 pwm_count pha1 1,2,4,8 0 1 s r (1) pwmase master m s res q shutdown blank1 pwmph2 pwmph2 pwmph2 pwmph2<4:0> pha2 s r (1) q shutdown blank2 ph1en ph2en ph1en ph2en pasen shutdown 5 5 5 rb7/sync rc1/an5/c12in1-/ph1 rc4/c2out/ph2 note 1: reset dominant.
? 2008 microchip technology inc. ds41249e-page 93 pic16f785/hv785 register 13-1: pwmcon0: pwm control register 0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 prsen pasen blank2 blank1 sync1 sync0 ph2en ph1en bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 prsen: pwm restart enable bit 1 = upon auto-shutdown, the pwmase shutdown bit clears automatically once the shutdown condi- tion goes away. the pwm restarts automatically. 0 = upon auto-shutdown, the pwmase must be cleared in firmware to restart the pwm. bit 6 pasen: pwm auto-shutdown enable bit 0 = pwm auto-shutdown is disabled 1 =v il on int pin will cause auto-shutdown event bit 5 blank2: ph2 blanking bit (1) 1 = the ph2 pin is active for a minimum of 1/2 of an f osc clock period after it is set 0 = the ph2 pin is reset as soon as the comparator trigger is active bit 4 blank1: ph1 blanking bit (1) 1 = the ph1 pin is active for a minimum of 1/2 of an f osc clock period after it is set 0 = the ph1 pin is reset as soon as the comparator trigger is active bit 3-2 sync<1:0>: sync pin function bits 0x = sync pin not used for pwm. pwm acts as its own master. rb7/sync pin is available for gen- eral purpose i/o. 10 = sync pin acts as system slave, receiving the pwm counter reset pulse 11 = sync pin acts as system master, driving the pwm counter reset pulse bit 1 ph2en: ph2 pin enabled bit 1 = the ph2 pin is driven by the pwm signal 0 = the ph2 pin is not used for pwm functions bit 0 ph1en: ph1 pin enabled bit 1 = the ph1 pin is driven by the pwm signal 0 = the ph1 pin is not used for pwm functions note 1: blanking is disabled when operating in complementary mode. see comod<1:0> bits in the pwmcon1 register (register 13-5) for more information.
pic16f785/hv785 ds41249e-page 94 ? 2008 microchip technology inc. register 13-2: pwmclk: pwm clock control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pwmase pwmp1 pwmp0 per4 per3 per2 per1 per0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 pwmase: pwm auto-shutdown event status bit 0 = pwm outputs are operating 1 = a shutdown event has occured. pwm outputs are inactive. bit 6-5 pwmp<1:0>: pwm clock prescaler bits 00 =pwm_clk = f osc 1 01 =pwm_clk = f osc 2 10 =pwm_clk = f osc 4 11 =pwm_clk = f osc 8 bit 4-0 per<4:0>: pwm period bits 00000 = not used. (period = 1/pwm_clk) 00001 = period = 2/pwm_clk2 0???? =? ? ? 01111 = period = 16/pwm_clk 10000 = period = 17/pwm_clk 1???? =? ? ? 11110 = period = 31/pwm_clk 11111 = period = 32/pwm_clk
? 2008 microchip technology inc. ds41249e-page 95 pic16f785/hv785 register 13-3: pwmph1: pwm phase 1 control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pol c2en c1en ph4 ph3 ph2 ph1 ph0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 pol: ph1 output polarity bit 1 = ph1 pin is active-low 0 = ph1 pin is active-high bit 6 c2en: comparator 2 enable bit when comod<1:0> = 00 (1) 1 = ph1 is reset when c2out goes high 0 = ph1 ignores comparator 2 when comod<1:0> = x1 (1) 1 = complementary drive terminates when c2out goes high 0 = comparator 2 is ignored when comod<1:0> = 10 (1) c2en has no effect bit 5 c1en: comparator 1 enable bit when comod<1:0> = 00 (1) 1 = ph1 is reset when c1out goes high 0 = ph1 ignores comparator 1 when comod<1:0> = x1 (1) 1 = complementary drive terminates when c1out goes high 0 = comparator 1 is ignored when comod<1:0> = 10 (1) c1en has no effect bit 4-0 ph<4:0>: pwm phase bits when comod<1:0> = 00 (1) 00000 = ph1 starts 1 pwm_clk period after falling edge of sync pulse. all other ph1 delays are expressed relative to this time. 00001 = ph1 is delayed by 1 pwm_clk pulse ????? =? ? ? 11111 = ph1 is delayed by 31 pwm_clk pulses when comod<1:0> = x1 or 1x (1) 00000 = complementary drive starts 1 pwm_clk period after falling edge of sync pulse. all other delays are expressed relative to this time. 00001 = complementary drive start is delayed by 1 pwm_clk pulse ????? =? ? ? 11111 = complementary drive start is delayed by 31 pwm_clk pulses note 1: see pwmcon1 register (register 13-5).
pic16f785/hv785 ds41249e-page 96 ? 2008 microchip technology inc. register 13-4: pwmph2: pwm phase 2 control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pol c2en c1en ph4 ph3 ph2 ph1 ph0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 pol: ph2 output polarity bit 1 = ph2 pin is active low 0 = ph2 pin is active high bit 6 c2en: comparator 2 enable bit when comod<1:0> = 00 (1) 1 = ph2 is reset when c2out goes high 0 = ph2 ignores comparator 2 when comod<1:0> = 1x or x1 (1) c2en has no effect bit 5 c1en: comparator 1 enable bit when comod<1:0> = 00 (1) 1 = ph2 is reset when c1out goes high 0 = ph2 ignores comparator 1 when comod<1:0> = 1x or x1 (1) c1en has no effect bit 4-0 ph<4:0>: pwm phase bits when comod<1:0> = 00 (1) 00000 = ph2 starts 1 pwm_clk period after falling edge of sync pulse. all other ph2 delays are expressed relative to this time. 00001 = ph2 is delayed by 1 pwm_clk pulse ????? =? ? ? 11111 = ph2 is delayed by 31 pwm_clk pulses when comod<1:0> = 1x (1) 00000 = complementary drive terminates 1 pwm_clk period after falling edge of sync pulse. all other ph2 delays are expressed relative to this time. 00001 = complementary drive termination is delayed by 1 pwm_clk pulse ????? =? ? ? 11111 = complementary drive termination is delayed by 31 pwm_clk pulses when comod<1:0> = 01 (1) ph<4:0> has no effect. note 1: see pwmcon1 register (register 13-5).
? 2008 microchip technology inc. ds41249e-page 97 pic16f785/hv785 figure 13-2: two-phase pwm aut o-shutdown and sync timing figure 13-3: two-phase pwm start-up timing 01 01 2 3 01 2 3 0 f osc sync pwm_count pwm_clk shutdown pha1 pha2 phase1 setup: ph<4:0> = 0x00, c1en = 1 , blank1 = 0 phase2 setup: ph<4:0> = 0x02, c2en = 1 , blank2 = 1 pwmp<1:0> = 0 x 01, per<4:0> = 0 x 03 pwm_clk 01 2 01 2 3 01 2 pwm_count 0 master slave 3 2 0 1 2 3 01 f osc sync pwm_count pwm_clk phnen phnen pwmp<1:0> = 0 x 01, per<4:0> = 0 x 03 pwm_clk 0 1 2 01 2 pwm_count 3 master slave 0 2 3
pic16f785/hv785 ds41249e-page 98 ? 2008 microchip technology inc. 13.7 example single phase application figure 13-4 shows an example of a single phase buck voltage regulator application. the pwm output drives q1 with pulses to alternately charge and discharge l1. c4 holds the charge from l1 during the inactive cycle of the drive period. r4 and c3 form a ramp generator. at the beginning of the pwm period, the pwm output goes high causing the voltage on c3 to rise concur- rently with the current in l1. when the voltage across c3 reaches the threshold level present at the positive input of comparator 1, the comparator output changes and terminates the drive output from the pwm to q1. when q1 is not driven, the current path to l1 through q1 is interrupted, but since the current in l1 cannot stop instantly, the current continues to flow through d2 as l1 discharges into c4. d1 quickly discharges c3 in preparation of the next ramp cycle. resistor divider r5 and r6 scale the output voltage, which is inverted and amplified by op amp 1, relative to the reference voltage present at the non-inverting pin of the op amp. r3, c5 and c2 form the inverting stabi- lization gain feedback of the amplifier. the vr refer- ence supplies a stable reference to the non-inverting input of the op amp, which is tweaked by the voltage source created by a secondary time based pwm output of the ccp and r1 and c1. output regulation occurs by the following principle: if the regulator output voltage is too low, then the voltage to the non-inverting input of comparator 1 will rise, resulting in a higher threshold voltage and, conse- quently, longer pwm drive pulses into q1. if the output voltage is too high, then the voltage to the non-inverting input of comparator 1 will fall, resulting in shorter pwm drive pulses into q1. figure 13-4: example sing le phase application v unreg opa1 ccp vr pic16f785 fet driver f osc r1 r2 c1 r3 c2 r4 d1 d2 l1 q1 c3 c4 r5 r6 c5 t wo -phase pwm ph1 c1
? 2008 microchip technology inc. ds41249e-page 99 pic16f785/hv785 13.8 pwm configuration when configuring the two-phase pwm, care must be taken to avoid active output levels from the ph1 and ph2 pins before the pwm is fully configured. the following sequence is suggested before the trisc register or any of the two-phase pwm control registers are first configured: ? output inactive (off) levels to the portc rc1/ an5/c12in1-/ph1 and rc4/c2out/ph2 pins. ? clear trisc bits 1 and 4 to configure the ph1 and ph2 pins as outputs. ? configure the pwmclk, pwmph1, pwmph2, and pwmcon1 registers. ? configure the pwmcon0 register. example 13-1: pwm setup example ;example to configure ph1 as a free running pwm output using the sync output as the duty cycle ;termination feedback. ;this requires an external connection between the sync output and the comparator input. ;sync out = rb7 on pin 10 ;c1 inverting input = rc2/an6 on pin 14 ;configure ph1, ph2 and sync pins as outputs ;first, ensure output latches are low bcf portc,1 ;ph1 low bcf portc,4 ;ph2 low bcf portb,7 ;sync low ;configure the i/os as outputs banksel trisb bcf trisc,1 ;ph1 output bcf trisc,4 ;ph2 output bcf trisb,7 ;sync output ;ph1 shares its function with an5 ;configure an5 as digital i/o bcf ansel0,5 ;an5 is digital, all others default as analog ;configure the pwm but don't enable ph1 or ph2 yet banksel pwmclk ;pwm control setup movlw b'00001100' ;auto shutdown off, no blanking, sync on, ph1 and ph2 off movwf pwmcon0 ;see data sheet page 93 ;pwm clock setup movlw b'00111101' ;pwm_clk = fosc, 30 clocks in pwm period movwf pwmclk ;see data sheet page 94 ;ph1 setup movlw b'00101111' ;non-inverted, terminate on c1, start on clock 15 movwf pwmph1 ;see data sheet page 95 ;ph2 setup movlw b'00110101' ;non-inverted, terminate on c1, start on clock 21 movwf pwmph2 ;see data sheet page 96 ;configure comparator 1 movlw b'10011110' ;c1 on, internal, inverted, normal speed, +:c1v ref , -:an6 movwf cm1con0 ;see data sheet page 68 ;configure comparator voltage reference banksel vrcon movlw b'10101100' ;c1v ren on, low range, cv ref = v dd /2 movwf vrcon ;see data sheet page 72 ;everything is setup at this point so now it is time to enable ph1 banksel pwmcon0 bsf pwmcon0,ph1en ;enable ph1 ;module is running autonomously at this point
pic16f785/hv785 ds41249e-page 100 ? 2008 microchip technology inc. 13.9 complementary output mode the two-phase pwm module may be configured to operate in a complementary output mode where ph1 and ph2 are always 180 degrees out-of-phase (see figure 13-5). three complementary modes are available and are selected by the comod<1:0> bits in the pwmcon1 register (see register 13-5). the differ- ence between the modes is the method by which the ph1 and ph2 outputs switch from the active to the inactive state during the pwm period. in complementary mode, there are three methods by which the duty cycle can be controlled. these modes are selected with the comod<1:0> bits (see register 13-5). in each of these modes, the duty cycle is started when the pwm_count = pwmph1<4:0> and terminates on one of the following: ? feedback through c1 or c2 ? when the pwm_count equals pwmph1<4:0> ? combined feedback and pwm_count match when comod<1:0> = 01 , the duty cycle is controlled only by feedback through comparator c1 or c2. in this mode, the active drive cycle starts when pwm_count equals pwmph1<4:0> and terminates when compara- tor c1?s output goes high (if enabled by pwmph1<5> = 1 ) or when comparator c2 output goes high (if enabled by pwmph1<6> = 1 ). when comod<1:0> = 10 , the duty cycle is controlled only by the pwm phase counter. in this mode, the active drive cycle starts when the pwm_count equals pwmph1<4:0> and terminates when the pwm_count equals pwmph2<4:0>. for example, free running 50% duty cycle can be accomplished by setting comod<1:0> = 10 and choosing appropriate values for pwmph1<4:0> and pwmph2<4:0>. when comod<1:0> = 11 , the duty cycle is controlled by the phase counter or feedback through comparator c1 or c2. for example, in this mode, the maximum duty cycle is determined by the values of pwmph1<4:0> (duty cycle start) and pwmph2<4:0> (duty cycle end). the duty cycle can be terminated earlier than the maximum by feedback through comparator c1 or c2. 13.9.1 dead band control the complementary output mode facilitates driving series connected mosfet drivers by providing dead band drive timing between each phase output (see figure 13-6). dead band times are selectable by the cmdly<4:0> bits of the pwmcon1 register. delays from 0 to 155 nanoseconds (typical) with a resolution of 5 nanoseconds (typical) are available. 13.9.2 overlap control overlap timing can be accomplished by configuring the complementary mode for the desired output polarity and overlap time (as dead time) then swapping the out- put connections and inverting the outputs. for exam- ple, to configure a complementary drive for 55 ns of overlap and an active-high drive output on ph1 and an active-low drive output on ph2, set the pwm control registers as follows: ? connect ph1 driver to ph2 output ? connect ph2 driver to ph1 output ? initialize portc<1> to 1 (ph2 driver off) ? initialize portc<4> to 0 (ph1 driver off) ? set trisc<1,4> to 0 for output ? set pwmph1 to 1 (inverted ph1) ? set pwmph2 to 1 (non-inverted ph2) ? set pwmcon1 for 55 ns delay and desired termination (comparator, count or both) ? set pwmcon0 desired sync and auto-shutdown configuration and to enable ph1 and ph2 13.9.3 shutdown in complementary mode during shutdown the ph1 and ph2 complementary outputs are forced to their inactive states (see figure 13-5). when shutdown ceases the pwm out- puts revert to their start-up states for the first cycle which is ph1 inactive (output undriven) and ph2 active (output driven).
? 2008 microchip technology inc. ds41249e-page 101 pic16f785/hv785 register 13-5: pwmcon1: pwm control register 1 figure 13-5: complementary output pwm block diagram u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? comod1 comod0 cmdly4 cmdly3 cmdly2 cmdly1 cmdly0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6-5 comod<1:0>: complementary mode select bits (1) 00 = normal two-phase operation. complementary mode is disabled. 01 = complementary operation. duty cycle is terminated by c1out or c2out. 10 = complementary operation. duty cycle is terminated by pwmph2<4:0> = pwm_count. 11 = complementary operation. duty cycle is terminated by pwmph2<4:0> = pwm_count or c1out or c2out. bit 4-0 cmdly<4:0>: complementary drive dead time bits (typical) 00000 =delay = 0 00001 = delay = 5 ns 00010 = delay = 10 ns ????? =? ? ? 11111 = delay = 155 ns note 1: pwmcon0<1:0> must be set to ? 11 ? for complementary mode operation. prescale pwmph1 pwmph1 pwmph2<4:0> pwmph2 pwmph1 pwmph1<4:0> f osc c1out c2out ps<1:0> pwm_clk pha1 pha2 pwm_reset delay s r (1) q 01 10 delay s r (1) q comod<1:0> cmdly<4:0> 5 5 11 rc1/an5/c12in1-/ph1 rc4/c2out/ph2 phase counter per<4:0> 5 pwm_count 0 1 pwmase master m s res ph1en ph2en pasen 5 rb7/sync 5 5 pwm_reset shutdown shutdown note 1: reset dominant.
pic16f785/hv785 ds41249e-page 102 ? 2008 microchip technology inc. figure 13-6: complementary output pwm timing table 13-1: registers/bits associated with pwm name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets cm1con0 c1on c1out c1oe c1pol c1sp c1r c1ch1 c1ch0 0000 0000 0000 0000 cm2con0 c2on c2out c2oe c2pol c2sp c2r c2ch1 c2ch0 0000 0000 0000 0000 pwmclk pwmase pwmp1 pwmp0 per4 per3 per2 per1 per0 0000 0000 0000 0000 pwmcon0 prsen pasen blank2 blank1 sync1 sync0 ph2en ph1en 0000 0000 0000 0000 pwmcon1 ? comod1 comod0 cmdly4 cmdly3 cmdly2 cmdly1 cmdly0 -000 0000 -000 0000 pwmph1 pol c2en c1en ph4 ph3 ph2 ph1 ph0 0000 0000 0000 0000 pwmph2 pol c2en c1en ph4 ph3 ph2 ph1 ph0 0000 0000 0000 0000 refcon ? ? bgst vrbb vren vroe cvroe ? --00 000- --00 000- vrcon c1vren c2vren vrr ? vr3 vr2 vr1 vr0 000- 0000 000- 0000 legend: x = unknown, u = unchanged, ? = unimplemented read as ? 0 ?, q = value depends upon condition. shaded cells are not used by data pwm module. 01 23 0 1 1 23 01 f osc sync pwm_count pwm_clk c1out pha1 pha2 phase 1 setup: ph<4:0> = 0x00, c1en = 1 , blankx = x , comod<1:0> = 0x01 pwmp<1:0> = 0 x 01, per<4:0> = 0 x 03 3 delay delay shutdown 0
? 2008 microchip technology inc. ds41249e-page 103 pic16f785/hv785 14.0 data eeprom memory the eeprom data memory is readable and writable during normal operation (full v dd range). this memory is not directly mapped in the register file space. instead, it is indirectly addressed through the special function registers. there are four sfrs used to read and write this memory: ? eecon1 ? eecon2 (not a physically implemented register) ? eedat ? eeadr eedat holds the 8-bit data for read/write, and eeadr holds the address of the eeprom location being accessed. the pic16f785/hv785 has 256 bytes of data eeprom with an address range from 0h to ffh. the eeprom data memory allows byte read and write. a byte write automatically erases the location and writes the new data (erase before write). the eeprom data memory is rated for high erase/write cycles. the write time is controlled by an on-chip timer. the write time will vary with voltage and temperature, as well as from chip-to-chip. please refer to ac specifications in section 19.0 ?electrical specifications? for exact limits. when the data memory is code-protected, the cpu may continue to read and write the data eeprom memory. the device programmer can no longer access the data eeprom data and will read zeroes. register 14-1: eedat: eeprom data register register 14-2: eeadr: eeprom address register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eedat7 eedat6 eedat5 eedat4 eedat3 eedat2 eedat1 eedat0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 eedatn : byte value to write to or read from data eeprom bits r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eeadr7 eeadr6 eeadr5 eeadr4 eeadr3 eeadr2 eeadr1 eeadr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 eeadr : specifies one of 256 locations for eeprom read/write operation bits
pic16f785/hv785 ds41249e-page 104 ? 2008 microchip technology inc. 14.1 eecon1 and eecon2 registers eecon1 is the control register with four low-order bits physically implemented. the upper four bits are non- implemented and read as ? 0 ?s. control bits rd and wr initiate read and write, respectively. these bits cannot be cleared, only set in software. they are cleared in hardware at completion of the read or write operation. the inability to clear the wr bit in software prevents the accidental, premature termination of a write operation. the wren bit, when set, will allow a write operation. on power-up, the wren bit is clear. the wrerr bit is set when a write operation is interrupted by a mclr reset, or a wdt time-out reset during normal operation. in these situations, following reset, the user can check the wrerr bit, clear it and rewrite the loca- tion. the eedat and eeadr registers are cleared by a reset. therefore, the eedat and eeadr registers will need to be re-initialized. interrupt flag eeif bit of the pir1 register is set when write is complete. this bit must be cleared in software. eecon2 is not a physical register. reading eecon2 will read all ? 0 ?s. the eecon2 register is used exclusively in the data eeprom write sequence. register 14-3: eecon1: eepr om control register note: the eecon1, eedat and eeadr registers should not be modified during a data eeprom write (wr bit = 1 ). u-0 u-0 u-0 u-0 r/w-x r/w-0 r/s-0 r/s-0 ? ? ? ? wrerr wren wr rd bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 iunimplemented: read as ? 0 ? bit 3 wrerr: eeprom error flag bit 1 = a write operation is prematurely terminated (any mclr reset, any wdt reset during normal operation or bor reset) 0 = the write operation completed bit 2 wren: eeprom write enable bit 1 = allows write cycles 0 = inhibits write to the data eeprom bit 1 wr: write control bit 1 = initiates a write cycle (the bit is cleared by hardware once write is complete. the wr bit can only be set, not cleared, in software.) 0 = write cycle to the data eeprom is complete bit 0 rd: read control bit 1 = initiates an eeprom read (read takes one cycle. rd is cleared in hardware. the rd bit can only be set, not cleared, in software.) 0 = does not initiate an eeprom read
? 2008 microchip technology inc. ds41249e-page 105 pic16f785/hv785 14.2 reading the eeprom data memory to read a data memory location, the user must write the address to the eeadr register and then set control bit rd of the eecon1 register, as shown in example 14- 1. the data is available, in the very next cycle, in the eedat register. therefore, it can be read in the next instruction. eedat holds this value until another read, or until it is written to by the user (during a write operation). example 14-1: data eeprom read 14.3 writing to the eeprom data memory to write an eeprom data location, the user must first write the address to the eeadr register and the data to the eedat register. then the user must follow a specific sequence to initiate the write for each byte, as shown in example 14-2. example 14-2: data eeprom write the write will not initiate if the sequence in example 14-2 is not followed exactly (write 55h to eecon2, write aah to eecon2, then set wr bit) for each byte. it is strongly recommended that interrupts be disabled during this code segment. a cycle count is executed during the required sequence. any number that is not equal to the required cycles to execute the required sequence will prevent the data from being written into the eeprom. additionally, the wren bit in eecon1 must be set to enable write. this mechanism prevents accidental writes to data eeprom due to errant (unexpected) code execution (i.e., lost programs). the user should keep the wren bit clear at all times, except when updating the eeprom. the wren bit is not cleared by hardware. after a write sequence has been initiated, clearing the wren bit will not affect this write cycle. the wr bit will be inhibited from being set unless the wren bit is set. at the completion of the write cycle, the wr bit is cleared in the hardware and the ee write complete interrupt flag bit (eeif) is set. the user can either enable this interrupt or poll this bit. the eeif bit of the pir1 register must be cleared by software. 14.4 write verify depending on the application, good programming practice may dictate that the value written to the data eeprom should be verified (see example 14-3) to the desired value to be written. example 14-3: write verify 14.4.1 using the data eeprom the data eeprom is a high-endurance, byte address- able array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). when variables in one section change frequently, while vari- ables in another section do not change, it is possible to exceed the total number of write cycles to the eeprom (specification d124) without exceeding the total number of write cycles to a single byte (specifica- tions d120 and d120a). if this is the case, then a refresh of the array must be performed. for this reason, variables that change infrequently (such as constants, ids, calibration, etc.) should be stored in flash program memory. 14.5 protect against spurious write there are conditions when the user may not want to write to the data eeprom memory. to protect against spurious eeprom writes, various mechanisms have been built in. on power-up, wren is cleared. also, the power-up timer (64 ms duration) prevents eeprom write. the write initiate sequence and the wren bit helps prevent an accidental write during a brown-out, power glitch and software malfunction. bsf status,rp0 ;bank 1 bcf status,rp1 ; movlw config_addr ; movwf eeadr ;address to read bsf eecon1,rd ;ee read movf eedat,w ;move data to w bsf status,rp0 ;bank 1 bcf status,rp1 ; bsf eecon1,wren ;enable write bcf intcon,gie ;disable ints btfsc intcon,gie ;see an-576 goto $-2 ; movlw 55h ;unlock write movwf eecon2 ; movlw aah ; movwf eecon2 ; bsf eecon1,wr ;start the write bsf intcon,gie ;enable ints sequence required bsf status,rp0 ;bank 1 bcf status,rp1 ; movf eedat,w ;eedat not changed from previous write bsf eecon1,rd ;yes, read the ; value written xorwf eedat,w ; btfss status,z ;is data the same goto write_err ;no, handle error ;yes, continue
pic16f785/hv785 ds41249e-page 106 ? 2008 microchip technology inc. 14.6 data eeprom operation during code-protect data memory can be code-protected by programming the cpd bit in the configuration word (register 15.2) to ? 0 ?. when the data memory is code-protected, the cpu is able to read and write data to the data eeprom. it is recommended that the user code protect the program memory when code protecting the data memory. this prevents anyone from programming zeroes over the existing code (which will execute as nop s) to reach an added routine, programmed in unused program mem- ory, which outputs the contents of data memory. programming unused locations in program memory to ? 0 ? will also help prevent data memory code protection from becoming breached. table 14-1: registers/bits associated with data eeprom name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets eeadr eeadr7 eeadr6 eeadr5 eeadr4 eeadr3 eeadr2 eeadr1 eeadr0 0000 0000 0000 0000 eecon1 ? ? ? ? wrerr wren wr rd ---- x000 ---- q000 eecon2 eeprom control register 2 (not a physical register) ---- ---- ---- ---- eedat eedat7 eedat6 eedat5 eedat4 eedat3 eedat2 eedat1 eedat0 0000 0000 0000 0000 intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 pie1 eeie adie ccp1ie c2ie c1ie osfie tmr2ie tmr1ie 0000 0000 0000 0000 pir1 eeif adif ccp1if c2if c1if osfif tmr2if tmr1if 0000 0000 0000 0000 legend: x = unknown, u = unchanged, ? = unimplemented read as ? 0 ?, q = value depends upon condition. shaded cells are not used by data eeprom module.
? 2008 microchip technology inc. ds41249e-page 107 pic16f785/hv785 15.0 special features of the cpu the pic16f785/hv785 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power sav- ing features and offer code protection. these features are: ? reset: - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) ? interrupts ? watchdog timer (wdt) ? oscillator selection ? sleep ? code protection ? id locations ? in-circuit serial programming? (icsp?) the pic16f785/hv785 has two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power-up timer (pwrt), which provides a fixed delay of 64 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabi- lizes. there is also circuitry to reset the device if a brown-out occurs, which can use the power-up timer to provide at least a 64 ms reset. with these three functions on-chip, most applications need no external reset circuitry. the sleep mode is designed to offer a very low-current power-down mode. the user can wake-up from sleep through an external reset, watchdog timer wake-up or interrupt. several oscillator options are also made available to allow the part to fit the application. the intosc option saves system cost, while the lp crystal option saves power. a set of configuration bits are used to select various options (see register 15.2). 15.1 configuration bits the configuration bits can be programmed (read as ? 0 ?), or left unprogrammed (read as ? 1 ?) to select various device configurations as shown in register 15.2. these bits are mapped in program memory location 2007h. note: address 2007h is beyond the user program memory space. it belongs to the special configuration memory space (2000h- 3fffh), which can be accessed only during programming. see ? pic16f785/hv785 memory programming specification ? (ds41237) for more information.
pic16f785/hv785 ds41249e-page 108 ? 2008 microchip technology inc. register 15-1: config : configuration word u-0 u-0 u-0 u-0 r/p-0 r/p-0 r/p-1 r/p-1 ? ? ? ? fcmen ieso boren1 boren0 bit 15 bit 8 r/p-0 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 cpd cp mclre pwrte wdte fosc2 fosc1 fosc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 13-12 fcmen: fail-safe clock monitor enabled bit (5) 1 = fail-safe clock monitor is enabled 0 = fail-safe clock monitor is disabled bit 10 ieso: internal external switchover bit 1 = internal external switchover mode is enabled 0 = internal external switchover mode is disabled bit 9-8 boren<1:0>: brown-out reset selection bits (1) 11 = bor enabled 10 = bor enabled during operation and disabled in sleep 01 = bor controlled by sboren bit (pcon<4>) 00 = bor disabled bit 7 cpd : data code protection bit (2), (3) 1 = data memory code protection is disabled 0 = data memory code protection is enabled bit 6 cp : code protection bit (2) 1 = program memory code protection is disabled 0 = program memory code protection is enabled bit 5 mclre: ra3/mclr pin function select bit (4) 1 = ra3/mclr pin function is mclr 0 = ra3/mclr pin function is digital input, mclr internally tied to v dd bit 4 pwrte : power-up timer enable bit 1 = pwrt disabled 0 = pwrt enabled bit 3 wdte: watchdog timer enable bit (5) 1 = wdt enabled 0 = wdt disabled and can be enabled by swdten bit (wdtcon<0>) bit 2-0 fosc<2:0>: oscillator selection bits 111 = rc oscillator: clkout function on ra4/an3/t1g/osc2/clkout pin, rc on ra5/t1cki/osc1/clkin 110 = rcio oscillator: i/o function on ra4/an3/t1g/osc2/clkout pin, rc on ra5/t1cki/osc1/clkin 101 = intosc oscillator: clkout function on ra4/an3/t1g/osc2/clkout pin, i/o function on ra5/t1cki/osc1/clkin 100 = intoscio oscillator: i/o function on ra4/an3/t1g/osc2/clkout pin, i/o function on ra5/t1cki/osc1/clkin 011 = ec: i/o function on ra4/an3/t1g/osc2/clkout pin, clkin on ra5/t1cki/osc1/clkin 010 = hs oscillator: high-speed crystal/resonator on ra4/an3/t1g/osc2/clkout and ra5/t1cki/osc1/clkin (5) 001 = xt oscillator: crystal/resonator on ra4/an3/t1g/osc2/clkout and ra5/t1cki/osc1/clkin (5) 000 = lp oscillator: low-power crystal on ra4/an3/t1g/osc2/clkout and ra5/t1cki/osc1/clkin (5) note 1: enabling brown-out reset does not automatically enable power-up timer. 2: program memory bulk erase must be performed to turn off code protection. 3: the entire data eeprom will be erased when the code protection is turned off. 4: when mclr is asserted in intosc or rc mode, the internal clock oscillator is disabled. 5: if the hs, xt, or lp oscillator fails in fail-safe mode the watchdog time-out can occur only once after which it will be disabl ed until the oscillator is restored.
? 2008 microchip technology inc. ds41249e-page 109 pic16f785/hv785 15.2 reset the pic16f785/hv785 differentiates between various kinds of reset: ? power-on reset (por) ? wdt reset during normal operation ? wdt reset during sleep ?mclr reset during normal operation ?mclr reset during sleep ? brown-out reset (bor) some registers are not affected in any reset condition; their status is unknown on por and unchanged in any other reset. most other registers are reset to a ?reset state? on: ? power-on reset ?mclr reset ?mclr reset during sleep ?wdt reset ? brown-out reset (bor) they are not affected by a wdt wake-up since this is viewed as the resumption of normal operation. to and pd bits are set or cleared differently in different reset situations, as indicated in table 15-2. these bits are used in software to determine the nature of the reset. see table 15-4 for a full description of reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 15-1. the mclr reset path has a noise filter to detect and ignore small pulses. see section 19.0 ?electrical specifications? for pulse width specifications. figure 15-1: simplified block di agram of on-chip reset circuit s r q external reset mclr /v pp pin v dd osc1/ wdt module v dd rise detect ost/pwrt lfintosc wdt time-out power-on reset ost 10-bit ripple counter pwrt chip_reset 11-bit ripple counter reset enable ost enable pwrt s leep brown-out (1) reset sboren boren clki pin note 1: refer to the configuration word register (register 15.2).
pic16f785/hv785 ds41249e-page 110 ? 2008 microchip technology inc. 15.2.1 power-on reset the on-chip por circuit holds the chip in reset until v dd has reached a high enough level for proper operation. a minimum rise rate for v dd is required. see section 19.0 ?electrical specifications? for details. if the bor is enabled, the minimum rise rate specifica- tion does not apply. the bor circuitry will keep the device in reset until v dd reaches v bor (see section 15.2.4 ?brown-out reset (bor)? ) the por circuit, on this device, has a por re-arm cir- cuit. this circuit is designed to ensure a re-arm of the por circuit if v dd drops below a preset re-arming volt- age (v parm ) for at least the minimum required time. once v dd is below the re-arming point for the minimum required time, the por reset will reactivate and remain in reset until v dd returns to a value greater than v por. at this point, a 1 s (typical) delay will be ini- tiated to allow v dd to continue to ramp to a voltage safely above v por. when the device starts normal operation (exits the reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. for additional information, refer to application note an607, ? power-up trouble shooting? (ds00607). 15.2.2 master clear (mclr ) pic16f785/hv785 has a noise filter in the mclr reset path. the filter will detect and ignore small pulses. it should be noted that a wdt reset does not drive mclr pin low. the behavior of the esd protection on the mclr pin has been altered from earlier devices of this family. voltages applied to the pin that exceed its specification can result in both mclr resets and excessive current beyond the device specification during the esd event. for this reason, microchip recommends that the mclr pin no longer be tied directly to v dd . the use of an rc network, as shown in figure 15-1, is suggested. figure 15-2: recommended mclr circuit an internal mclr option is enabled by clearing the mclre bit in the configuration word. when cleared, mclr is internally tied to v dd and an internal weak pull-up is enabled for the mclr pin. the v pp function of the ra3/mclr /v pp pin is not affected by selecting the internal mclr option. 15.2.3 power-up timer (pwrt) the power-up timer provides a fixed 64 ms (nominal) time out on power-up only, from por or brown-out reset. the power-up timer operates from the 31 khz lfintosc oscillator. for more information, see section 3.4 ?internal clock modes? . the chip is kept in reset as long as pwrt is active. the pwrt delay allows the v dd to rise to an acceptable level. a config- uration bit, pwrte can disable (if ? 1 ?) or enable (if ? 0 ?) the power-up timer. the power-up timer should be enabled when brown-out reset is enabled, although it is not required. the power-up time delay will vary from chip-to-chip and vary due to: ?v dd variation ? temperature variation ? process variation see dc parameters for details ( section 19.0 ?electrical specifications? ). 15.2.4 brown-out reset (bor) the boren0 and boren1 bits in the configuration word select one of four bor modes. two modes have been added to allow software or hardware control of the bor enable. when boren<1:0> = 01 , the sbo- ren bit of the pcon register enables/disables the bor allowing it to be controlled in software. by select- ing boren<1:0>, the bor is automatically disabled in sleep to conserve power, and enabled on wake-up. in this mode, the sboren bit is disabled. see register 15.2 for the configuration word definition. if v dd falls below v bor for greater than parameter (t bor ), see section 19.0 ?electrical specifica- tions? , the brown-out situation will reset the device. this will occur regardless of the v dd slew rate. a reset is not assured if v dd falls below v bor for less than parameter (t bor ). on any reset (power-on, brown-out reset, watchdog, etc.), the chip will remain in reset until v dd rises above v bor (see figure 15-3). the power-up timer will now be invoked, if enabled, and will keep the chip in reset an additional 64 ms. if v dd drops below v bor while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be re-initialized. once v dd rises above v bor , the power-up timer will execute a 64 ms reset. v dd ra3/mclr /v pp r1 1k ( or greater) c1 0.1 f (optional, not critical) pic16f785/hv785 note: the power-up timer is enabled by the pwrte bit in the configuration word.
? 2008 microchip technology inc. ds41249e-page 111 pic16f785/hv785 15.2.5 bor calibration the pic16f785/hv785 stores the bor calibration values in fuses located in the calibration word (2008h). the calibration word is not erased when using the specified bulk erase sequence in the ?pic16f785/ hv785 memory programming specification ? (ds41237) and thus, does not require reprogramming. figure 15-3: brown-out situations note: address 2008h is beyond the user program memory space. it belongs to the special configuration memory space (2000h- 3fffh), which can be accessed only during programming. see ? pic16f785/hv785 memory programming specification ? (ds41237) for more information. 64 ms (1) v bor v dd internal reset v bor v dd internal reset 64 ms (1) <64 ms 64 ms (1) v bor v dd internal reset note 1: 64 ms delay only if pwrte bit is programmed to ? 0 ?.
pic16f785/hv785 ds41249e-page 112 ? 2008 microchip technology inc. 15.2.6 time-out sequence on power-up, the time-out sequence is as follows: first, pwrt time out is invoked after por has expired, then ost is activated after the pwrt time out has expired. the total time out will vary based on oscillator configu- ration and pwrte bit status. for example, in ec mode with pwrte bit equal to ? 1 ? (pwrt disabled), there will be no time out at all. figure 15-4, figure 15-6 and figure 15-6 depict time-out sequences. the device can execute code from the intosc, while ost is active by enabling two-speed start-up or fail-safe monitor (see section 3.6.2 ?two-speed start-up sequence? and section 3.7 ?fail-safe clock monitor? ). since the time outs occur from the por pulse, if mclr is kept low long enough, the time outs will expire. then bringing mclr high will begin execution immediately (see figure 15-6). this is useful for testing purposes or to synchronize more than one pic16f785/hv785 device operating in parallel. table 15-5 shows the reset conditions for some special registers, while table 15-4 shows the reset conditions for all the registers. 15.2.7 power co ntrol (pcon) register the power control register (address 8eh) has two sta- tus bits to indicate what type of reset that last occurred. bit 0 is bor (brown-out reset). bor is unknown on power-on reset. it must then be set by the user and checked on subsequent resets to see if bor = 0 , indicating that a brown-out has occurred. the bor status bit is a ?don?t care? and is not necessarily predictable if the brown-out circuit is disabled (boren<1:0> = 00 in the configuration word). bit 1 is por (power-on reset). it is ? 0 ? on power-on reset and unaffected otherwise. the user must write a ? 1 ? to this bit following a power-on reset. on a subsequent reset, if por is ? 0 ?, it will indicate that a power-on reset has occurred (i.e., v dd may have gone too low). for more information, see section 15.2.4 ?brown-out reset (bor)? . table 15-1: time out in various situations table 15-2: status/pcon bits and their significance table 15-3: summary of regist ers associated with brown-out oscillator configuration power-up brown-out reset wake-up from sleep pwrte = 0 pwrte = 1 pwrte = 0 pwrte = 1 xt, hs, lp t pwrt + 1024?t osc 1024?t osc t pwrt + 1024?t osc 1024?t osc 1024?t osc rc, ec, intosc t pwrt ?t pwrt ?? por bor to pd condition 0x11 power-on reset u011 brown-out reset uu0u wdt reset uu00 wdt wake-up uuuu mclr reset during normal operation uu10 mclr reset during sleep legend: u = unchanged, x = unknown name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets pcon ? ? ?sboren ? ?por bor ---1 --qq ---1 --qq status irp rp1 rp0 to pd z dc c 0001 1xxx 0001 1xxx legend: u = unchanged, x = unknown, ? = unimplemented bit, reads as ? 0 ?, q = value depends on condition. shaded cells are not used by bor. note 1: other (non power-up) resets include mclr reset and watchdog timer reset during normal operation.
? 2008 microchip technology inc. ds41249e-page 113 pic16f785/hv785 figure 15-4: time-out sequence on power-up (delayed mclr ): case 1 figure 15-5: time-out sequence on power-up (delayed mclr ): case 2 figure 15-6: time-out sequ ence on power-up (mclr with v dd ) t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset
pic16f785/hv785 ds41249e-page 114 ? 2008 microchip technology inc. table 15-4: initialization condition for registers register address power-on reset mclr reset wdt reset brown-out reset (1) wake-up from sleep through interrupt wake-up from sleep through wdt time-out w? xxxx xxxx uuuu uuuu uuuu uuuu indf 00h/80h xxxx xxxx xxxx xxxx uuuu uuuu tmr0 01h xxxx xxxx uuuu uuuu uuuu uuuu pcl 02h/82h 0000 0000 0000 0000 pc + 1 (3) status 03h/83h 0001 1xxx 000q quuu (4) uuuq quuu (4) fsr 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu porta 05h --x0 x000 (6) --u0 u000 (7) --uu uuuu portb 06h xx00 ---- (6) uu00 ---- (7) uuuu ---- portc 07h 00xx 0000 (6) 00uu uuuu (7) uuuu uuuu pclath 0ah/8ah ---0 0000 ---0 0000 ---u uuuu intcon 0bh/8bh 0000 0000 0000 0000 uuuu uuuu (2) pir1 0ch 0000 0000 0000 0000 uuuu uuuu (2) tmr1l 0eh xxxx xxxx uuuu uuuu uuuu uuuu tmr1h 0fh xxxx xxxx uuuu uuuu uuuu uuuu t1con 10h 0000 0000 uuuu uuuu uuuu uuuu tmr2 11h 0000 0000 0000 0000 uuuu uuuu t2con 12h -000 0000 -000 0000 -uuu uuuu ccpr1l 13h xxxx xxxx uuuu uuuu uuuu uuuu ccpr1h 14h xxxx xxxx uuuu uuuu uuuu uuuu ccp1con 15h --00 0000 --00 0000 --uu uuuu wdtcon 18h ---0 1000 ---0 1000 ---u uuuu adresh 1eh xxxx xxxx uuuu uuuu uuuu uuuu adcon0 1fh 0000 0000 0000 0000 uuuu uuuu option_reg 81h 1111 1111 1111 1111 uuuu uuuu trisa 85h --11 1111 --11 1111 --uu uuuu trisb 86h 1111 ---- 1111 ---- uuuu ---- trisc 87h 1111 1111 1111 1111 uuuu uuuu pie1 8ch 0000 0000 0000 0000 uuuu uuuu pcon 8eh ---1 --0x ---u --uq (1,5) ---u --uu osccon 8fh -110 q000 -110 q000 -uuu uuuu osctune 90h ---0 0000 ---u uuuu ---u uuuu ansel0 91h 1111 1111 1111 1111 uuuu uuuu pr2 92h 1111 1111 1111 1111 1111 1111 ansel1 93h ---- 1111 ---- 1111 ---- uuuu wpua 95h --11 1111 --11 1111 --uu uuuu ioca 96h --00 0000 --00 0000 --uu uuuu refcon 98h --00 000- --00 000- --uu uuu- legend: u = unchanged, x = unknown, ? = unimplemented bit, reads as ? 0 ?, q = value depends on condition. note 1: if v dd goes too low, power-on reset will be activated and registers will be affected differently. 2: one or more bits in intcon and/or pir1 will be affected (to cause wake-up). 3: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 4: see table 15-5 for reset value for specific condition. 5: if reset was due to brown-out, then bit 0 = 0 . all other resets will cause bit 0 = u . 6: analog channels read 0 but data latches are unknown. 7: analog channels read 0 but data latches are unchanged.
? 2008 microchip technology inc. ds41249e-page 115 pic16f785/hv785 vrcon 99h 000- 0000 000- 0000 uuu- uuuu eedat 9ah 0000 0000 0000 0000 uuuu uuuu eeadr 9bh 0000 0000 0000 0000 uuuu uuuu eecon1 9ch ---- x000 ---- q000 ---- uuuu eecon2 9dh ---- ---- ---- ---- ---- ---- adresl 9eh xxxx xxxx uuuu uuuu uuuu uuuu adcon1 9fh -000 ---- -000 ---- -uuu ---- pwmcon1 110h -000 0000 -000 0000 -uuu uuuu pwmcon0 111h 0000 0000 0000 0000 uuuu uuuu pwmclk 112h 0000 0000 0000 0000 uuuu uuuu pwmph1 113h 0000 0000 0000 0000 uuuu uuuu pwmph2 114h 0000 0000 0000 0000 uuuu uuuu cm1con0 119h 0000 0000 0000 0000 uuuu uuuu cm2con0 11ah 0000 0000 0000 0000 uuuu uuuu cm2con1 11bh 00-- --10 00-- --10 uu-- --uu opa1con 11ch 0--- ---- 0--- ---- u--- ---- opa2con 11dh 0--- ---- 0--- ---- u--- ---- table 15-4: initialization condition for registers (continued) register address power-on reset mclr reset wdt reset brown-out reset (1) wake-up from sleep through interrupt wake-up from sleep through wdt time-out legend: u = unchanged, x = unknown, ? = unimplemented bit, reads as ? 0 ?, q = value depends on condition. note 1: if v dd goes too low, power-on reset will be activated and registers will be affected differently. 2: one or more bits in intcon and/or pir1 will be affected (to cause wake-up). 3: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 4: see table 15-5 for reset value for specific condition. 5: if reset was due to brown-out, then bit 0 = 0 . all other resets will cause bit 0 = u . 6: analog channels read 0 but data latches are unknown. 7: analog channels read 0 but data latches are unchanged.
pic16f785/hv785 ds41249e-page 116 ? 2008 microchip technology inc. table 15-5: initialization condi tion for special registers condition program counter status register pcon register power-on reset 000h 0001 1xxx ---1 --0x mclr reset during normal operation 000h 000u uuuu ---u --uu mclr reset during sleep 000h 0001 0uuu ---u --uu wdt reset 000h 0000 uuuu ---u --uu wdt wake-up pc + 1 uuu0 0uuu ---u --uu brown-out reset 000h 0001 1uuu ---1 --u0 interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---u --uu legend: u = unchanged, x = unknown, ? = unimplemented bit, reads as ? 0 ?. note 1: when the wake-up is due to an interrupt and global enable bit gie is set, the pc is loaded with the interrupt vector (0004h) after execution of pc + 1.
? 2008 microchip technology inc. ds41249e-page 117 pic16f785/hv785 15.3 interrupts the pic16f785/hv785 has 11 sources of interrupt: ? external interrupt ra2/int ? tmr0 overflow interrupt ? porta change interrupt ? 2 comparator interrupts ? a/d interrupt ? timer1 overflow interrupt ? timer2 match interrupt ? eeprom data write interrupt ? fail-safe clock monitor interrupt ? ccp interrupt the interrupt control register (intcon) and peripheral interrupt register (pir1) record individual interrupt requests in flag bits. the intcon register also has individual and global interrupt enable bits. a global interrupt enable bit, gie of the intcon reg- ister enables (if set) all unmasked interrupts, or dis- ables (if cleared) all interrupts. individual interrupts can be disabled through their corresponding enable bits in intcon register and pie1 register. gie is cleared on reset. the return from interrupt instruction, retfie , exits interrupt routine, as well as sets the gie bit, which re-enables unmasked interrupts. the following interrupt flags are contained in the int- con register: ? int pin interrupt ? porta change interrupt ? tmr0 overflow interrupt the peripheral interrupt flags are contained in the special register pir1. the corresponding interrupt enable bit is contained in special register pie1. the following interrupt flags are contained in the pir1 register: ? eeprom data write interrupt ? a/d interrupt ? 2 comparator interrupts ? timer1 overflow interrupt ? timer2 match interrupt ? fail-safe clock monitor interrupt ? ccp interrupt when an interrupt is serviced: ? the gie is cleared to disable any further interrupt ? the return address is pushed onto the stack ? the pc is loaded with 0004h for external interrupt events, such as the int pin or porta change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends upon when the interrupt event occurs (see figure 15-8). the latency is the same for one or two- cycle instructions. once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. for additional information on timer1, timer2, comparators, a/d, data eeprom or ccp modules, refer to the respective peripheral section. note 1: individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the gie bit. 2: when an instruction that clears the gie bit is executed, any interrupts that were pending for execution in the next cycle are ignored. the interrupts, which were ignored, are still pending to be serviced when the gie bit is set again.
pic16f785/hv785 ds41249e-page 118 ? 2008 microchip technology inc. 15.3.1 ra2/an2/t0cki/int/c1out interrupt external interrupt on ra2/an2/t0cki/int/c1out pin is edge-triggered; either rising, if intedg bit of the option register is set, or falling, if intedg bit is clear. when a valid edge appears on the ra2/an2/ t0cki/int/c1out pin, the intf bit of the intcon register is set. this interrupt can be disabled by clear- ing the inte control bit of the intcon register. the intf bit must be cleared in software in the interrupt service routine before re-enabling this interrupt. the ra2/an2/t0cki/int/c1out interrupt can wake-up the processor from sleep if the inte bit was set prior to going into sleep. the status of the gie bit decides whether or not the processor branches to the interrupt vector following wake-up (0004h). see section 15.6 ?power-down mode (sleep)? for details on sleep and figure 15-10 for timing of wake-up from sleep through ra2/an2/t0cki/int/c1out interrupt. 15.3.2 tmr0 interrupt an overflow (ffh 00h) in the tmr0 register will set the t0if bit of the intcon register. the interrupt can be enabled/disabled by setting/clearing t0ie bit of the intcon register. see section 5.0 ?timer0 module? for operation of the timer0 module. 15.3.3 porta interrupt an input change on porta change sets the raif of the intcon register bit. the interrupt can be enabled/ disabled by setting/clearing the raie bit of the intcon register. plus, individual pins can be configured through the ioca register. figure 15-7: interrupt logic note: the ansel0 (91h), and ansel1 (93h) registers must be initialized to configure an analog channel as a digital input. pins configured as analog inputs will read ? 0 ?. note: if a change on the i/o pin should occur when the read operation is being executed (start of the q2 cycle), then the raif inter- rupt flag may not get set. tmr1if tmr1ie c1if c1ie t0if t0ie intf inte raif raie gie peie wake-up (if in sleep mode) (1) interrupt to cpu eeie eeif adif adie ioc-ra0 ioca0 ioc-ra1 ioca1 ioc-ra2 ioca2 ioc-ra3 ioca3 ioc-ra4 ioca4 ioc-ra5 ioca5 tmr2if tmr2ie ccp1if ccp1ie osfif osfie c2if c2ie note 1: some peripherals depend upon the system clock for operation. since the system clock is suspended during sleep, only those peripherals which do not depend upon the system clock will wake the part from sleep. see section 15.6.1 ?wake-up from sleep? .
? 2008 microchip technology inc. ds41249e-page 119 pic16f785/hv785 figure 15-8: int pin interrupt timing table 15-6: summary of interrupt registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 pie1 eeie adie ccp1ie c2ie c1ie osfie tmr2ie tmr1ie 0000 0000 0000 0000 pir1 eeif adif ccp1if c2if c1if osfif tmr2if tmr1if 0000 0000 0000 0000 legend: x = unknown, u = unchanged, ? = unimplemented read as ? 0 ?, q = value depends upon conditi on. shaded cells are not used by the interrupt module. q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 clkout int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed interrupt latency pc pc + 1 pc + 1 0004h 0005h inst (0004h) inst (0005h) dummy cycle inst (pc) inst (pc + 1) inst (pc - 1) inst (0004h) dummy cycle inst (pc) ? note 1: intf flag is sampled here (every q1). 2: asynchronous interrupt latency = 3-4 t cy . synchronous latency = 3 t cy , where t cy = instruction cycle time. latency is the same whether inst (pc) is a single cycle or a 2-cycle instruction. 3: clkout is available only in intosc and rc oscillator modes. 4: for minimum width of int pulse, refer to ac specifications in section 19.0 ?electrical specifications? . 5: intf is enabled to be set any time during the q4-q1 cycles. (1) (2) (3) (4) (5) (1)
pic16f785/hv785 ds41249e-page 120 ? 2008 microchip technology inc. 15.4 context saving during interrupts during an interrupt, only the return pc value is saved on the stack. typically, users may wish to save key registers during an interrupt (e.g., w and status registers). this must be implemented in software. since the last 16 bytes of all banks are common in the pic16f785/hv785 (see figure 2-2), temporary hold- ing registers w_temp and status_temp should be placed in here. these 16 locations do not require banking, therefore, making it easier to save and restore context. the same code shown in example 15-1 can be used to: ? store the w register ? store the status register ? execute the isr code ? restore the status (and bank select bit register) ? restore the w register example 15-1: saving status and w registers in ram note: the pic16f785/hv785 normally does not require saving the pclath. however, if computed goto ?s are used in the isr and the main code, the pclath must be saved and restored in the isr. movwf w_temp ;copy w to temp register swapf status,w ;swap status to be saved into w (swap does not affect status) clrf status ;bank 0, regardless of current bank, clears irp,rp1,rp0 movwf status_temp ;save status to bank zero status_temp register : :(isr) ;insert user code here : swapf status_temp,w ;swap status_temp register into w ;(sets bank to original state) movwf status ;move w into status register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w
? 2008 microchip technology inc. ds41249e-page 121 pic16f785/hv785 15.5 watchdog timer (wdt) for pic16f785/hv785, the wdt has been modified from previous pic16fxxx devices. the new wdt is code and functionally compatible with previous pic16fxxx wdt modules and adds a 16-bit prescaler to the wdt. this allows the user to scale the value for the wdt and tmr0 at the same time. in addition, the wdt time out value can be extended to 268 seconds. wdt is cleared under certain conditions described in table 15-7. 15.5.1 wdt oscillator the wdt derives its time base from the 31 khz lfin- tosc. the lts bit does not reflect that the lfintosc is enabled (oscon<1>). the value of wdtcon is ? ---0 1000 ? on all resets. this gives a nominal time base of 16 ms, which is compatible with the time base generated with previous pic16fxxx microcontroller versions. a new prescaler has been added to the path between the intrc and the multiplexers used to select the path for the wdt. this prescaler is 16 bits and can be programmed to divide the intrc by 128 to 65536, giving the time base used for the wdt a nominal range of 1 ms to 268s. 15.5.2 wdt control the wdte bit is located in the configuration word. when set, the wdt runs continuously. when the wdte bit in the configuration word register is set, the swdten bit of the wdtcon register has no effect. if wdte is clear, then the swdten bit can be used to enable and disable the wdt. setting the bit will enable it and clearing the bit will disable it. the psa and ps<2:0> bits of the option register have the same function as in previous versions of the pic16fxxx family of microcontrollers. see section 5.0 ?timer0 module? for more information. figure 15-9: watchdog timer bl ock diagram table 15-7: wdt status note: when the oscillator start-up timer (ost) is invoked, the wdt is held in reset, because the wdt ripple counter is used by the ost to perform the oscillator delay count. when the ost count has expired, the wdt will begin counting (if enabled). conditions wdt wdte = 0 cleared clrwdt command osc fail detected exit sleep + system clock = t1osc, extrc, intrc, extclk exit sleep + system clock = xt, hs, lp cleared until the end of ost 31 khz psa 16-bit wdt prescaler from tmr0 clock source 8 ps<2:0> psa wdt time-out to tmr0 wdtps<3:0> wdte from configuration word 1 1 0 0 swdten from wdtcon lfintosc clock note 1: this is the shared timer0/wdt prescaler. see section 5.4 ?prescaler? for more information. prescaler (1) 8-bit
pic16f785/hv785 ds41249e-page 122 ? 2008 microchip technology inc. register 15-2: wdtcon: watchdog ti mer control register table 15-8: summary of watchdog timer registers u-0 u-0 u-0 r/w-0 r/w-1 r/w-0 r/w-0 r/w-0 ? ? ? wdtps3 wdtps2 wdtps1 wdtps0 swdten (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 unimplemented: read as ? 0 ? bit 4-1 wdtps<3:0>: watchdog timer period select bits bit value = prescale rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 (reset value) 0101 = 1:1024 0110 = 1:2048 0111 = 1:4096 1000 = 1:8192 1001 = 1:16384 1010 = 1:32768 1011 = 1:65536 1100 = reserved 1101 = reserved 1110 = reserved 1111 = reserved bit 0 swdten: software enable or disable the watchdog timer bit (1) 1 = wdt is turned on 0 = wdt is turned off (reset value) note 1: if wdte configuration bit = 1 , then wdt is always enabled, irrespective of this control bit. if wdte con- figuration bit = 0 , then it is possible to turn wdt on/off with this control bit. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets option_reg rapu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 status irp rp1 rpo to pd z dc c 0001 1xxx 000q quuu wdtcon ? ? ? wdtps3 wdtps2 wstps1 wdtps0 swdten ---0 1000 ---0 1000 legend: shaded cells are not used by the watchdog timer. note 1: see register 15.2 for operation of all configuration word bits.
? 2008 microchip technology inc. ds41249e-page 123 pic16f785/hv785 15.6 power-down mode (sleep) the power-down mode is entered by executing a sleep instruction. if the watchdog timer is enabled: ? wdt will be cleared but keeps running ?pd bit in the status register is cleared ?to bit is set ? oscillator driver is turned off ? i/o ports maintain the status they had before sleep was executed (driving high, low or high- impedance). for lowest current consumption in this mode, all i/o pins should be either at v dd or v ss , with no external circuitry drawing current from the i/o pin and all unused peripheral modules should be disabled. digital i/o pins that are high-impedance inputs should be pulled high, or low, externally to avoid switching currents caused by floating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on-chip pull-ups on porta should be considered. the mclr pin must be at a logic high level. 15.6.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin 2. watchdog timer wake-up (if wdt was enabled) 3. interrupt from ra2/an2/t0cki/int/c1out pin, porta change or a peripheral interrupt. the first event will cause a device reset. the two latter events are considered a continuation of program exe- cution. the to and pd bits in the status register can be used to determine the cause of device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. to bit is cleared if wdt wake-up occurred. the following peripheral interrupts can wake the device from sleep: ? tmr1 interrupt; timer1 must be operating as an asynchronous counter. ? ccp capture mode interrupt ? a/d conversion (when a/d clock source is rc) ? eeprom write operation completion ? comparator output changes state ? interrupt-on-change ? external interrupt from int pin other peripherals cannot generate interrupts since, during sleep, no on-chip clocks are present. when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit (and peie bit where applicable) must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution of the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruc- tion, then branches to the interrupt address (0004h). in cases where the execution of the instruction, following sleep, is not desired, the user should place a nop after the sleep instruction. the wdt is cleared when the device wakes up from sleep, regardless of the source of wake-up. 15.6.2 wake-up using interrupts when global interrupts are disabled (i.e., gie bit of the intcon register is clear) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: ? if the interrupt occurs before the execution of a sleep instruction, the sleep instruction will complete as a nop . therefore, the wdt and wdt prescaler and postscaler (if enabled) will not be cleared, the to bit will not be set and the pd bit will not be cleared. ? if the interrupt occurs during or after the execu- tion of a sleep instruction, the device will immediately wake-up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt prescaler and postscaler (if enabled) will be cleared, the to bit will be set, and the pd bit will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . when global interrupts are disabled, a clrwdt instruction should be executed before a sleep instruction to ensure that the wdt is cleared. note: it should be noted that a reset generated by a wdt time-out does not drive mclr pin low. note: if the global interrupts are disabled (gie is cleared), but any interrupt source has both its interrupt enable bit and the correspond- ing interrupt flag bits set (including peie, where applicable), the device will immedi- ately wake-up from sleep. the sleep instruction is completely executed.
pic16f785/hv785 ds41249e-page 124 ? 2008 microchip technology inc. figure 15-10: wake-up from sleep through interrupt (1) 15.7 code protection if the code protection bit(s) have not been programmed, the on-chip program memory can be read out using icsp ? for verification purposes. 15.8 id locations four memory locations (2000h-2003h) are designated as id locations where the user can store checksum or other code identification numbers. these locations are not accessible during normal execution, but are readable and writable during program/verify. only the least significant 7 bits of the id locations are used. 15.9 in-circuit serial programming? (icsp?) the pic16f785/hv785 microcontrollers can be seri- ally programmed while in the end application circuit. this is simply done with five lines: ?clock ?data ?power ?ground ? programming voltage this allows customers to manufacture boards with unprogrammed devices and then program the micro- controller just before shipping the product. this also allows the most recent firmware, or a custom firmware, to be programmed. the device is placed into a program/verify mode by holding the ra0 and ra1 pins low, while raising the mclr (v pp ) pin from v il to v ihh . see the ?pic16f785/ hv785 memory programming specification ? (ds41237) for more information. ra0 becomes the programming data and ra1 becomes the programming clock. both ra0 and ra1 are schmitt trigger inputs in this mode. after reset, to place the device into program/verify mode, the program counter (pc) is at location 00h. a 6-bit command is then supplied to the device. depending on the command, 14 bits of program data are then supplied to or from the device, depending on whether the command was a load or a read. for complete details of serial programming, please refer to the ?pic16f785/hv785 memory programming speci- fication ? (ds41237). a typical in-circuit serial programming connection is shown in figure 15-11. q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout (4) int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc + 1 pc + 2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (3) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc + 2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024t osc (drawing not to scale). this delay does not apply to ec, rc and intosc oscillator modes or two-speed start-up (see section 3.6 ?two-speed clock start-up mode? ). 3: gie = 1 assumed. in this case after wake-up, the processor jumps to 0004h. if gie = 0 , execution will continue in-line. 4: clkout is not available in xt, hs, lp or ec oscillator modes, but shown here for timing reference. note: if the code protection is turned off, the entire data eeprom and flash program memory will be erased by performing a bulk erase command. see the ?pic16f785/hv785 memory program- ming specification ? (ds41237) for more information.
? 2008 microchip technology inc. ds41249e-page 125 pic16f785/hv785 figure 15-11: typical in-circuit serial programming connection 15.10 in-circuit debugger ? in-circuit debugging requires clock, data and mclr pins. a special 28-pin pic16f785-icd device is used with mplab ? icd 2 to provide separate clock, data and mclr pins so that no pins are lost for these functions, leaving all 18 of the pic16f785/hv785 i/o pins available to the user during debug operation. ? this special icd device is mounted on the top of a header and its signals are routed to the mplab icd 2 connector. on the bottom of the header is a 20-pin socket that plugs into the user?s target via the 20-pin stand-off connector. ? when the icd pin on the pic16f785-icd device is held low, the in-circuit debugger functionality is enabled. this function allows simple debugging functions when used with mplab icd 2. when the microcontroller has this feature enabled, some of the resources are not available for general use. table 15-9 shows which features are consumed by the background debugger. table 15-9: debugger resources for more information, see ? mplab ? icd 2 in-circuit debugger user?s guide ? (ds51331), available on microchip?s web site (www.microchip.com). figure 15-12: 28-pin icd pinout resource description i/o pins icdclk, icddata stack 1 level data ram 65h-70h, f0h program memory address 0h must be nop 700h-7ffh external connector signals to n o r m a l connections to normal connections v dd v ss mclr /v pp /ra3 ra1 ra0 +5.0v 0v v pp clk data i/o * * * * * isolation devices (as required) pic16f785 28-pin pdip pic16f785/hv785-icd in-circuit debug device shntreg icdmclr /v pp v dd ra5 ra4 ra3 icdclk icddata vss ra0 rc6 rb4 ra1 ra2 rc5 rc4 rc3 rc0 rc1 rc2 1 2 3 4 5 6 7 8 9 10 28 27 26 25 24 23 22 21 20 19 nc nc rc7 rb7 icd rb5 rb6 nc 11 12 13 14 18 17 16 15
pic16f785/hv785 ds41249e-page 126 ? 2008 microchip technology inc. 16.0 voltage regulator the pic16hv785 includes a permanent internal 5 volt (nominal) shunt regulator in parallel with the v dd pin. this eliminates the need for an external voltage regula- tor in systems sourced by an unregulated supply. all external devices connected directly to the v dd pin will share the regulated supply voltage and contribute to the total v dd supply current (i load ). 16.1 regulator operation the regulator operates by maintaining a constant voltage at the v dd pin by adjusting the regulator shunt current in response to variations of the v dd supply load and the unregulated supply voltage. the regulator behaves like a fully compensated zener diode. (see figure 16-1). figure 16-1: regulator an external current limiting resistor, r ser , located between the unregulated supply, v unreg , and the v dd pin, drops the difference in voltage between v unreg and v dd . r ser must be between r max and r min as defined by equation 16-1. equation 16-1: r ser limiting resistor 16.2 regulator precautions the total v dd load current variation must be less than 46 ma so that it falls within the voltage regulator shunt current dynamic range. if the load current rises above the expected maximum, the regulator will be starved for current and go out of regulation causing v dd to drop. since the regulator uses the band gap voltage as the regulated voltage reference, the vr voltage reference is permanently enabled in the pic16hv785 device. (use d on b lank pages to make page count even) v unreg r ser v dd to other circuitry pic16hv785 voltage regulator r max = (vu min - v dd ) ? 1000 1.05 ? (4 m a + i load ) r min = (vu min - v dd ) ? 1000 0.95 ? (50 m a) where: r max = maximum value of r ser (ohms) r min = minimum value of r ser (ohms) vu min = minimum value of v unreg vu max = maximum value of v unreg v dd = regulated voltage (5v nominal) i load = maximum expected load current in ma including i/o pin currents and external circuits connected to v dd . 1.05 = compensation for +5% tolerance of r ser 0.95 = compensation for -5% tolerance of r ser
? 2008 microchip technology inc. ds41249e-page 127 pic16f785/hv785 17.0 instruction set summary the pic16f785/hv785 instruction set is highly orthog- onal and is comprised of three basic categories: ? byte-oriented operations ? bit-oriented operations ? literal and control operations each pic16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the format for each of the categories is presented in figure 17-1, while the various opcode fields are summarized in table 17-1. table 17-2 lists the instructions recognized by the mpasm tm assembler. for byte-oriented instructions, ? f ? represents a file register designator and ? d ? represents a destination designator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if ? d ? is zero, the result is placed in the w register. if ? d ? is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, ? b ? represents a bit field designator, which selects the bit affected by the operation, while ? f ? represents the address of the file in which the bit is located. for literal and control operations, ? k ? represents an 8-bit or 11-bit constant, or literal value. one instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 mhz, this gives a normal instruction execution time of 1 s. all instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. when this occurs, the execution takes two instruction cycles, with the second cycle executed as a nop . all instruction examples use the format ?0xhh? to represent a hexadecimal number, where ?h? signifies a hexadecimal digit. 17.1 read-modify-write operations any instruction that specifies a file register as part of the instruction performs a read-modify-write (rmw) operation. the register is read, the data is modified, and the result is stored according to either the instruc- tion, or the destination designator ?d?. a read operation is always performed, even if the instruction is a write command. for example, a clrf porta instruction will read porta, clear all the data bits, then write the result back to porta. this example would have the unintended result of clearing the condition that set the raif flag. table 17-1: opcode field descriptions figure 17-1: general format for instructions note: to maintain upward compatibility with future products, do not use the option and tris instructions. field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don?t care location (= 0 or 1 ). the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 : store result in w, d = 1 : store result in file register f. default is d = 1. pc program counter to time-out bit pd power-down bit byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w d = 1 for destination f bit-oriented file register operations 13 10 9 7 6 0 b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 k = 8-bit immediate value 13 11 10 0 k = 11-bit immediate value general call and goto instructions only opcode d f (file #) f = 7-bit file register address opcode b (bit #) f (file #) opcode k (literal) opcode k (literal)
pic16f785/hv785 ds41249e-page 128 ? 2008 microchip technology inc. table 17-2: pic16f785/hv785 instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f ? f, d f, d f, d f, d f, d f, d f, d f ? f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1 (2) 1 1 (2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k ? k k k ? k ? ? k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z to ,pd z to ,pd c,dc,z z note 1: when an i/o register is modified as a function of itself (e.g., movf porta, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tm r0 register (and, where applicable, d = 1 ), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is modified, or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop .
? 2008 microchip technology inc. ds41249e-page 129 pic16f785/hv785 17.2 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 k 255 operation: (w) + k (w) status affected: c, dc, z description: the contents of the w register are added to the eight-bit literal ?k? and the result is placed in the w register. addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 127 d [0,1] operation: (w) + (f) (destination) status affected: c, dc, z description: add the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w) .and. (k) (w) status affected: z description: the contents of w register are and?ed with the eight-bit literal ?k?. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 127 d [0,1] operation: (w) .and. (f) (destination) status affected: z description: and the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 127 0 b 7 operation: 0 (f) status affected: none description: bit ?b? in register ?f? is cleared. bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 127 0 b 7 operation: 1 (f) status affected: none description: bit ?b? in register ?f? is set.
pic16f785/hv785 ds41249e-page 130 ? 2008 microchip technology inc. btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 127 0 b 7 operation: skip if (f) = 0 status affected: none description: if bit ?b? in register ?f? is ? 1 ?, the next instruction is executed. if bit ?b?, in register ?f?, is ? 0 ?, the next instruction is discarded, and a nop is executed instead, making this a two-cycle instruction. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 127 0 b < 7 operation: skip if (f) = 1 status affected: none description: if bit ?b? in register ?f? is ? 0 ?, the next instruction is executed. if bit ?b? is ? 1 ?, then the next instruc- tion is discarded and a nop is executed instead, making this a two-cycle instruction. call call subroutine syntax: [ label ] call k operands: 0 k 2047 operation: (pc)+ 1 tos, k pc<10:0>, (pclath<4:3>) pc<12:11> status affected: none description: call subroutine. first, return address (pc + 1) is pushed onto the stack. the eleven-bit immedi- ate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two-cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 f 127 operation: 00h (f) 1 z status affected: z description: the contents of register ?f? are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h (w) 1 z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h wdt 0 wdt prescaler, 1 to 1 pd status affected: to , pd description: clrwdt instruction resets the watchdog timer. it also resets the prescaler of the wdt. status bits to and pd are set.
? 2008 microchip technology inc. ds41249e-page 131 pic16f785/hv785 comf complement f syntax: [ label ] comf f,d operands: 0 f 127 d [0,1] operation: (f ) (destination) status affected: z description: the contents of register ?f? are complemented. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in regis- ter ?f?. decf decrement f syntax: [ label ] decf f,d operands: 0 f 127 d [0,1] operation: (f) - 1 (destination) status affected: z description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 127 d [0,1] operation: (f) - 1 (destination); skip if result = 0 status affected: none description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 1 ?, the next instruc- tion is executed. if the result is ? 0 ?, then a nop is executed instead, making it a two-cycle instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 k 2047 operation: k pc<10:0> pclath<4:3> pc<12:11> status affected: none description: goto is an unconditional branch. the eleven-bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two- cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 f 127 d [0,1] operation: (f) + 1 (destination) status affected: z description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 127 d [0,1] operation: (f) + 1 (destination), skip if result = 0 status affected: none description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 1 ?, the next instruc- tion is executed. if the result is ? 0 ?, a nop is executed instead, making it a two-cycle instruction.
pic16f785/hv785 ds41249e-page 132 ? 2008 microchip technology inc. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. k (w) status affected: z description: the contents of the w register are or?ed with the eight-bit literal ?k?. the result is placed in the w register. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 127 d [0,1] operation: (w) .or. (f) (destination) status affected: z description: inclusive or the w register with register ?f?. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. movf move f syntax: [ label ] movf f,d operands: 0 f 127 d [0,1] operation: (f) (dest) status affected: z encoding: 00 1000 dfff ffff description: the contents of register ?f? is moved to a destination depen- dent upon the status of ?d?. if ?d? = 0 , destination is w register. if ?d? = 1 , the destination is file register ?f? itself. ?d? = 1 is useful to test a file register since status flag z is affected. movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k (w) status affected: none encoding: 11 00xx kkkk kkkk description: the eight-bit literal ?k? is loaded into w register. the ?don?t cares? will assemble as 0 ?s . movwf move w to f syntax: [ label ] movwf f operands: 0 f 127 operation: (w) (f) status affected: none encoding: 00 0000 1fff ffff description: move data from w register to register ?f?. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 00 0000 0xx0 0000 description: no operation.
? 2008 microchip technology inc. ds41249e-page 133 pic16f785/hv785 retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos pc, 1 gie status affected: none encoding: 00 0000 0000 1001 description: return from interrupt. stack is poped and top-of-stack (tos) is loaded in the pc. interrupts are enabled by setting global interrupt enable bit, gie of the intcon register. this is a two- cycle instruction. retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k (w); tos pc status affected: none encoding: 11 01xx kkkk kkkk description: the w register is loaded with the eight-bit literal ?k?. the pro- gram counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. return return from subroutine syntax: [ label ] return operands: none operation: tos pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two-cycle instruction. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 127 d [0,1] operation: see description below status affected: c encoding: 00 1101 dfff ffff description: the contents of register ?f? are rotated one bit to the left through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 127 d [0,1] operation: see description below status affected: c encoding: 00 1100 dfff ffff description: the contents of register ?f? are rotated one bit to the right through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ? the result is placed back in register ?f?. sleep go into standby mode syntax: [ labe l] sleep operands: none operation: 00h wdt, 0 wdt prescaler, 1 to , 0 pd status affected: to , pd encoding: 00 0000 0110 0011 description: the power-down status bit, pd is cleared. time out status bit, to is set. watchdog timer and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. register f c register f c
pic16f785/hv785 ds41249e-page 134 ? 2008 microchip technology inc. sublw subtract w from literal syntax: [ label ]sublw k operands: 0 k 255 operation: k - (w) ( w) status affected: c, dc, z encoding: 11 110x kkkk kkkk description: the w register is subtracted (2?s complement method) from the eight-bit literal ?k?. the result is placed in the w register. c = 1 ; result is positive or zero c = 0 ; result is negative subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 127 d [0,1] operation: (f) - (w) ( dest) status affected: c, dc, z encoding: 00 0010 dfff ffff description: subtract (2?s complement method) w register from register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. c = 1 ; result is positive or zero c = 0 ; result is negative swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 127 d [0,1] operation: (f<3:0>) (dest<7:4>), (f<7:4>) (dest<3:0>) status affected: none encoding: 00 1110 dfff ffff description: the upper and lower nibbles of register ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in w register. if ?d? is ? 1 ?, the result is placed in register ?f?. tris load tris register syntax: [ label ] tris f operands: 5 f 6 operation: (w) tris register f; status affected: none encoding: 00 0000 0110 0fff description: the instruction is supported for code compatibility with the pic16c5x products. since tris registers are readable and writable, the user can directly address them. words: 1 cycles: 1 example: to maintain upward compati- bility with future pic ? products, do not use this instruction. xorlw exclusive or literal with w syntax: [ label ]xorlw k operands: 0 k 255 operation: (w) .xor. k ( w) status affected: z encoding: 11 1010 kkkk kkkk description: the contents of the w register are xor?ed with the eight-bit literal ?k?. the result is placed in the w register.
? 2008 microchip technology inc. ds41249e-page 135 pic16f785/hv785 xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 127 d [0,1] operation: (w) .xor. (f) ( dest) status affected: z encoding: 00 0110 dfff ffff description: exclusive or the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ? the result is stored back in register ?f?.
pic16f785/hv785 ds41249e-page 136 ? 2008 microchip technology inc. notes:
? 2008 microchip technology inc. ds41249e-page 137 pic16f785/hv785 18.0 development support the pic ? microcontrollers are supported with a full range of hardware and software development tools: ? integrated development environment - mplab ? ide software ? assemblers/compilers/linkers - mpasm tm assembler - mplab c18 and mplab c30 c compilers -mplink tm object linker/ mplib tm object librarian - mplab asm30 assembler/linker/library ? simulators - mplab sim software simulator ?emulators - mplab ice 2000 in-circuit emulator - mplab real ice? in-circuit emulator ? in-circuit debugger - mplab icd 2 ? device programmers - picstart ? plus development programmer - mplab pm3 device programmer - pickit? 2 development programmer ? low-cost demonstration and development boards and evaluation kits 18.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. the mplab ide is a windows ? operating system-based application that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? visual device initializer for easy register initialization ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select third party tools, such as hi-tech software c compilers and iar c compilers the mplab ide allows you to: ? edit your source files (either assembly or c) ? one touch assemble (or compile) and download to pic mcu emulator and simulator tools (automatically updates all project information) ? debug using: - source files (assembly or c) - mixed assembly and c - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power.
pic16f785/hv785 ds41249e-page 138 ? 2008 microchip technology inc. 18.2 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for all pic mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 18.3 mplab c18 and mplab c30 c compilers the mplab c18 and mplab c30 code development systems are complete ansi c compilers for microchip?s pic18 and pic24 families of microcon- trollers and the dspic30 and dspic33 family of digital signal controllers. these compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 18.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 18.5 mplab asm30 assembler, linker and librarian mplab asm30 assembler produces relocatable machine code from symbolic assembly language for dspic30f devices. mplab c30 c compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire dspic30f instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility 18.6 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c18 and mplab c30 c compilers, and the mpasm and mplab asm30 assemblers. the software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
? 2008 microchip technology inc. ds41249e-page 139 pic16f785/hv785 18.7 mplab ice 2000 high-performance in-circuit emulator the mplab ice 2000 in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for pic microcontrollers. software control of the mplab ice 2000 in-circuit emulator is advanced by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator system with enhanced trace, trigger and data monitor- ing features. interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. the architecture of the mplab ice 2000 in-circuit emulator allows expansion to support new pic microcontrollers. the mplab ice 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft ? windows ? 32-bit operating system were chosen to best make these features available in a simple, unified application. 18.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs pic ? flash mcus and dspic ? flash dscs with the easy-to-use, powerful graphical user interface of the mplab integrated development environment (ide), included with each kit. the mplab real ice probe is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with the popular mplab icd 2 system (rj11) or with the new high-speed, noise tolerant, low- voltage differential signal (lvds) interconnection (cat5). mplab real ice is field upgradeable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added, such as software break- points and assembly code trace. mplab real ice offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 18.9 mplab icd 2 in-circuit debugger microchip?s in-circuit debugger, mplab icd 2, is a powerful, low-cost, run-time development tool, connecting to the host pc via an rs-232 or high-speed usb interface. this tool is based on the flash pic mcus and can be used to develop for these and other pic mcus and dspic dscs. the mplab icd 2 utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip?s in-circuit serial programming tm (icsp tm ) protocol, offers cost- effective, in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by setting breakpoints, single step- ping and watching variables, and cpu status and peripheral registers. running at full speed enables testing hardware and applications in real time. mplab icd 2 also serves as a development programmer for selected pic devices. 18.10 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an sd/mmc card for file storage and secure data applications.
pic16f785/hv785 ds41249e-page 140 ? 2008 microchip technology inc. 18.11 picstart plus development programmer the picstart plus development programmer is an easy-to-use, low-cost, prototype programmer. it connects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer supports most pic devices in dip packages up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 18.12 pickit 2 development programmer the pickit? 2 development programmer is a low-cost programmer and selected flash device debugger with an easy-to-use interface for programming many of microchip?s baseline, mid-range and pic18f families of flash memory microcontrollers. the pickit 2 starter kit includes a prototyping development board, twelve sequential lessons, software and hi-tech?s picc? lite c compiler, and is designed to help get up to speed quickly using pic ? microcontrollers. the kit provides everything needed to program, evaluate and develop applications using microchip?s powerful, mid-range flash memory family of microcontrollers. 18.13 demonstration, development and evaluation boards a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. check the microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.
? 2008 microchip technology inc. ds41249e-page 141 pic16f785/hv785 19.0 electrical specifications absolute maximum ratings (?) ambient temperature under bias................................................................................................. ................ -40 to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on v dd with respect to v ss ............................................................................................................ -0.3 to +6.5v voltage on mclr with respect to vss ........................................................................................................-0 .3 to +13.5v voltage on rb6 open-drain pin with respect to vss ............................................................................. ........-0.3 to +8.5v voltage on all other pins with respect to v ss ................................................................................. -0.3v to (v dd + 0.3v) total power dissipation (1) (pdip and soic).........................................................................................................800 mw total power dissipation (1) (ssop) ........................................................................................................................ 600 mw maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ............................................................... ....................................................... 20 ma output clamp current, i ok (vo < 0 or vo >v dd ) ............................................................... ................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by porta, portb, and portc (combined) .................................................................200 ma maximum current sourced porta, portb, and portc (combined).................................................................200 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd ? i oh } + {(v dd ? v oh ) x i oh } + (v o l x i ol ). ? notice : stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. note: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 should be used when applying a ?low? level to the mclr pin, rather than pulling this pin directly to v ss .
pic16f785/hv785 ds41249e-page 142 ? 2008 microchip technology inc. figure 19-1: pic16f785/hv785 with analog disabled voltage-frequency graph, -40c t a +125c (2) 5.5 2.0 3.5 2.5 0 3.0 4.0 4.5 5.0 4 frequency (mhz) (2) v dd (volts) note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: frequency denotes system clock frequency. when using the hfintosc the system clock is after the postscaler. 3: the internal shunt regulator of the pic16hv785 keeps v dd at or below 5.0v (nominal). 816 12 20 10 (3)
? 2008 microchip technology inc. ds41249e-page 143 pic16f785/hv785 19.1 dc characteristics: pic16f785/hv785-i (industrial), pic16f785/hv785-e (extended) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. sym characteristic min typ? max units conditions d001 d001a d001b d001c d001d v dd supply voltage (2) 2.0 2.2 2.5 3.0 4.5 ? ? ? ? ? 5.5 5.5 5.5 5.5 5.5 v v v v v f osc 4 mhz: pic16f785 with a/d off pic16f785 with a/d on, 0c to +125c pic16f785 with a/d on, -40c to +125c 4 mhz f osc 10 mhz 10 mhz f osc 20 mhz d002 v dr ram data retention voltage (1) 1.5* ? ? v device in sleep mode d003 v por v dd voltage above which the internal por releases ?1.8? vsee section 15.2.1 ?power-on reset? for details. d003a v parm v dd voltage below which the internal por rearms ?1.0? vsee section 15.2.1 ?power-on reset? for details. d004 s vdd v dd rise rate to ensure internal power-on reset signal 0.05* ? ? v/ms see section 15.2.1 ?power-on reset? for details. d005 v bor brown-out reset ?2.1? v * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: maximum supply voltage is v shunt for pic16hv785 device (see table 19-14).
pic16f785/hv785 ds41249e-page 144 ? 2008 microchip technology inc. 19.2 dc characteristics: pic16f785/hv785-i (industrial) (1), (2) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device characteristics min typ? max units conditions v dd d010 supply current (i dd ) ?1123 a2.0f osc = 32 khz lp oscillator mode ?1838 a3.0 ?3575 a5.0 d011 ? 140 240 a2.0f osc = 1 mhz xt oscillator mode ? 220 380 a3.0 ? 380 550 a5.0 d012 ? 260 360 a2.0f osc = 4 mhz xt oscillator mode ? 420 650 a3.0 ? 0.8 1.1 ma 5.0 d013 ? 130 220 a2.0f osc = 1 mhz ec oscillator mode ? 215 360 a3.0 ? 360 520 a5.0 d014 ? 220 340 a2.0f osc = 4 mhz ec oscillator mode ? 375 550 a3.0 ?0.65 1 ma 5.0 d015 ? 8 20 a2.0f osc = 31 khz intrc mode ?1640 a3.0 ?3165 a5.0 d016 ? 340 450 a2.0f osc = 4 mhz intosc mode ? 500 700 a3.0 ? 800 1200 a5.0 d017 ? 230 400 a2.0f osc = 4 mhz extrc mode ? 400 680 a3.0 ? 0.63 1.1 ma 5.0 d018 ? 2.6 3.25 ma 4.5 f osc = 20 mhz hs oscillator mode ? 2.8 3.35 ma 5.0 ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. these paramet ers are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to- rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operati ng voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, inte rnal code execution pattern and temperat ure also have an impact on the current consumption. 3: the peripheral current is the sum of the base i dd or i pd and the additional current consumed when this peripheral is enabled. the peripheral current can be determined by subtracting the base i dd or i pd current from this limit. max values should be used when calculating total current consumption. 4: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd . when a/d is off, it will not consume any current other than leakage current. the power-down curr ent spec includes any such leakage from the a/d module.
? 2008 microchip technology inc. ds41249e-page 145 pic16f785/hv785 d020 power-down base current (i pd ) (4) ? 0.15 1.2 a 2.0 wdt, bor, comparators, v ref , t1osc, op amps and vr disabled ? 0.20 1.5 a3.0 ? 0.35 1.8 a5.0 d021 ? 1.7 3.0 a 2.0 wdt current (3) ?2 4 a3.0 ?3 7 a5.0 d022 ? 42 60 a 3.0 bor current (3) ? 85 122 a5.0 d023 ? 362 465 a 2.0 comparator current (3) cxsp = 1 ? 418 532 a3.0 ? 500 603 a5.0 d023a ? 96 125 a 2.0 comparator current (3) cxsp = 0 ? 112 142 a3.0 ? 132 162 a5.0 d024 ? 39 47 a2.0cv ref current (3) low range ?5972 a3.0 ? 98 124 a5.0 d024a ? 30 36 a2.0cv ref current (3) high range (v rr = 0 ) ?4555 a3.0 ?7595 a5.0 d025 ? 2.5 7.0 a 2.0 t1 o sc current (3) ?3.214 a3.0 ?4.832 a5.0 d026 ? 0.30 1.6 na 3.0 a/d current (3) (not converting) ? 0.36 1.9 na 5.0 d027 ? 9 13 a 2.0 vr current (3) ?1014 a3.0 ?1115 a5.0 d028 ? 202 370 a 3.0 op amp current (3) ? 217 418 a5.0 19.2 dc characteristics: pic16f785/hv785-i (industrial) (1), (2) (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device characteristics min typ? max units conditions v dd ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. these paramet ers are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to- rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operati ng voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, inter nal code execution pattern and temperature also have an impact on the current consumption. 3: the peripheral current is the sum of the base i dd or i pd and the additional current consumed when this peripheral is enabled. the peripheral current can be determined by subtracting the base i dd or i pd current from this limit. max values should be used when calculating total current consumption. 4: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd . when a/d is off, it will not consume any current other than leakage current. the power-down curr ent spec includes any such leakage from the a/d module.
pic16f785/hv785 ds41249e-page 146 ? 2008 microchip technology inc. 19.3 dc characteristics: pic16f785/hv785-e (extended) (1), (2) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40 c t a +125 c for extended param no. device characteristics min typ? max units conditions v dd d010e supply current (i dd ) ?1123 a2.0f osc = 32 khz lp oscillator mode ?1838 a3.0 ?3575 a5.0 d011e ? 140 240 a2.0f osc = 1 mhz xt oscillator mode ? 220 380 a3.0 ? 380 550 a5.0 d012e ? 260 360 a2.0f osc = 4 mhz xt oscillator mode ? 420 650 a3.0 ? 0.8 1.1 ma 5.0 d013e ? 130 220 a2.0f osc = 1 mhz ec oscillator mode ? 215 360 a3.0 ? 360 520 a5.0 d014e ? 220 340 a2.0f osc = 4 mhz ec oscillator mode ? 375 550 a3.0 ? 0.65 1.0 ma 5.0 d015e ? 8 20 a2.0f osc = 31 khz intrc mode ?1640 a3.0 ?3165 a5.0 d016e ? 340 450 a2.0f osc = 4 mhz intosc mode ? 500 700 a3.0 ? 800 1200 a5.0 d017e ? 230 400 a2.0f osc = 4 mhz extrc mode ? 400 680 a3.0 ? 0.63 1.1 ma 5.0 d018e ? 2.6 3.25 ma 4.5 f osc = 20 mhz hs oscillator mode ? 2.8 3.35 ma 5.0 ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. these paramet ers are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operati ng voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, inte rnal code execution pattern and temperat ure also have an impact on the current consumption. 3: the peripheral current is the sum of the base i dd or i pd and the additional current consumed when this peripheral is enabled. the peripheral current can be determined by subtracting the base i dd or i pd current from this limit. max values should be used when calculating total current consumption. 4: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd . when a/d is off, it will not consume any current other than leakage current. the power-down current spec includes any such leakage from the a/d module.
? 2008 microchip technology inc. ds41249e-page 147 pic16f785/hv785 d020e power-down base current (i pd ) (4) ?0.15 9 a 2.0 wdt, bor, comparators, v ref , t1osc, op amps and vr disabled ?0.2011 a3.0 ?0.3515 a5.0 d021e ? 1.7 17.5 a 2.0 wdt current (3) ?219 a3.0 ?322 a5.0 d022e ? 42 65 a 3.0 bor current (3) ? 85 127 a5.0 d023e ? 362 476 a 2.0 comparator current (3) cxsp = 1 ? 418 554 a3.0 ? 500 625 a5.0 d023e ? 96 130 a 2.0 comparator current (3) cxsp = 0 ? 112 147 a3.0 ? 132 168 a5.0 d024e ? 39 47 a2.0cv ref current (3) low range ?5972 a3.0 ? 98 124 a5.0 d024e ? 30 36 a2.0cv ref current (3) high range ?4555 a3.0 ?7595 a5.0 d025e ? 2.5 21 a 2.0 t1 o sc current (3) ?3.228 a3.0 ?4.845 a5.0 d026e ? 0.30 12 ua 3.0 a/d current (3) (not converting) ?0.3616 ua 5.0 d027e ? 9 20 a 3.0 vr current (3) ?1026 a3.0 ?1130 a5.0 d028e ? 202 417 a 3.0 op amp current (3) ? 217 468 a5.0 19.3 dc characteristics: pic16f785/hv785-e (extended) (1), (2) (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40 c t a +125 c for extended param no. device characteristics min typ? max units conditions v dd ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. these paramet ers are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operati ng voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, inter nal code execution pattern and temperature also have an impact on the current consumption. 3: the peripheral current is the sum of the base i dd or i pd and the additional current consumed when this peripheral is enabled. the peripheral current can be determined by subtracting the base i dd or i pd current from this limit. max values should be used when calculating total current consumption. 4: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd . when a/d is off, it will not consume any current other than leakage current. the power-down current spec includes any such leakage from the a/d module.
pic16f785/hv785 ds41249e-page 148 ? 2008 microchip technology inc. 19.4 dc characteristics: pic16f785/hv785-i (industrial), pic16f785/hv785-e (extended) dc characteristics standard operating conditions (unless otherwise stated) operating temperature-40c t a +85c for industrial -40c t a +125c for extended param no. sym characteristic min typ? max units conditions v il input low voltage i/o ports d030 with ttl buffer v ss ?0.8v4.5v v dd 5.5v d030a v ss ? 0.15 v dd v otherwise d031 with schmitt trigger buffer v ss ?0.2 v dd v entire range d032 mclr , osc1 (rc mode) (1) v ss ?0.2 v dd v d033 osc1 (xt and lp modes) v ss ?0.3v d033a osc1 (hs mode) v ss ?0.3 v dd v v ih input high voltage i/o ports ? d040 d040a with ttl buffer 2.0 (0.25 v dd + 0.8) ? ? v dd v dd v v 4.5v v dd 5.5v otherwise d041 with schmitt trigger buffer 0.8 v dd ?v dd v entire range d042 mclr 0.8 v dd ?v dd v d043 osc1 (xt and lp modes) 1.6 ? v dd v d043a osc1 (hs mode) 0.7 v dd ?v dd v d043b osc1 (rc mode) 0.9 v dd ?v dd v (note 1) d070 i pur porta weak pull-up current 50* 250 400* av dd = 5.0v, v pin = v ss i il input leakage current (2) d060 i/o ports ? 0 . 1 1 av ss v pin v dd , pin at high-impedance d060a analog inputs ? 0 . 1 1 av ss v pin v dd d060b v ref ? 0 . 1 1 av ss v pin v dd d061 mclr (3) ? 0 . 1 5 av ss v pin v dd d063 osc1 ? 0 . 1 5 av ss v pin v dd , xt, hs and lp osc configuration v ol output low voltage d080 i/o ports ? ? 0.6 v i ol = 8.5 ma, v dd = 4.5v d083 osc2/clkout (rc mode) ? ? 0.6 v i ol = 1.6 ma, v dd = 4.5v (ind.) i ol = 1.2 ma, v dd = 4.5v (ext.) v oh output high voltage d090 i/o ports v dd ? 0.7 ? ? v i oh = -3.0 ma, v dd = 4.5v d092 osc2/clkout (rc mode) v dd ? 0.7 ? ? v i oh = -1.3 ma, v dd = 4.5v (ind.) i oh = -1.0 ma, v dd = 4.5v (ext.) d193* v od open-drain high voltage ? ? 8.5 v rb6 pin * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. these paramete rs are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended to use an external clock in rc mode. 2: negative current is defined as current sourced by the pin. 3: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 4: see section 14.4.1 ?using the data eeprom? on page 105.
? 2008 microchip technology inc. ds41249e-page 149 pic16f785/hv785 capacitive loading specs on output pins d100 cosc2 osc2 pin ? ? 15* pf in xt, hs and lp modes when external clock is used to drive osc1 d101 c io all i/o pins ? ? 50* pf data eeprom memory d120 e d byte endurance 100k 1m ? e/w -40 c t a +85c d120a e d byte endurance 10k 100k ? e/w +85c t a +125c d121 v drw v dd for read/write v min ? 5.5 v using eecon1 to read/write v min = minimum operating voltage d122 t dew erase/write cycle time ? 5 6 ms d123 t retd characteristic retention 40 ? ? year provided no other specifications are violated d124 t ref number of total erase/write cycles before refresh (4) 1m 10m ? e/w -40 c t a +85c program flash memory d130 e p cell endurance 10k 100k ? e/w -40 c t a +85c d130a e p cell endurance 1k 10k ? e/w +85c t a +125c d131 v pr v dd for read v min ?5.5vv min = minimum operating voltage d132 v pew v dd for erase/write 4.5 ? 5.5 v d133 t pew erase/write cycle time ? 2 2.5 ms d134 t retd characteristic retention 40 ? ? year provided no other specifications are violated 19.4 dc characteristics: pic16f785/hv785-i (industrial), pic16f785/hv785-e (extended) (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature-40c t a +85c for industrial -40c t a +125c for extended param no. sym characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended to use an external clock in rc mode. 2: negative current is defined as current sourced by the pin. 3: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 4: see section 14.4.1 ?using the data eeprom? on page 105.
pic16f785/hv785 ds41249e-page 150 ? 2008 microchip technology inc. 19.5 timing parameter symbology the timing parameter symbols have been created with one of the following formats: figure 19-2: load conditions 1. tpps2pps 2. tpps t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (high-impedance) v valid l low z high-impedance v dd /2 c l r l pin pin v ss v ss c l r l =464 c l = 50 pf for all pins 15 pf for osc2 output load condition 1 load condition 2 legend:
? 2008 microchip technology inc. ds41249e-page 151 pic16f785/hv785 figure 19-3: exter nal clock timing table 19-1: external clock timing requirements param no. sym characteristic min typ? max units conditions f osc external clkin frequency (1) ? 32.768 ? khz lp mode (complementary input only) dc ? 4 mhz xt mode dc ? 20 mhz hs mode dc ? 20 mhz ec mode oscillator frequency (1) ? 32.768 ? khz lp osc mode ?4 ?mhzintosc mode dc ? 4 mhz rc osc mode 0.1 ? 4 mhz xt osc mode 1? 20mhzhs osc mode 1 t osc external clkin period (1) ?0.3052 ? s lp mode (complementary input only) 50 ? ns hs osc mode 50 ? ns ec osc mode 250 ? ns xt osc mode oscillator period (1) ?0.3052 ? slp osc mode ?250 ? nsintosc mode 250 ? ? ns rc osc mode 250 ? 10,000 ns xt osc mode 50 ? 1,000 ns hs osc mode 2t cy instruction cycle time (1) 200 t cy dc ns t cy = 4/f osc 3 tosl, to sh external clkin (osc1) high external clkin low 2* ? ? slp oscillator, t osc l/h duty cycle 20* ? ? ns hs oscillator, t osc l/h duty cycle 100 * ? ? ns xt oscillator, t osc l/h duty cycle 4tosr, to sf external clkin rise external clkin fall ? ? 50* ns lp oscillator ? ? 25* ns xt oscillator ? ? 15* ns hs oscillator * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min? values with an external clock applied to osc1 pin. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices. osc1 clkout q4 q1 q2 q3 q4 q1 1 2 3 3 4 4
pic16f785/hv785 ds41249e-page 152 ? 2008 microchip technology inc. figure 19-4: clkout and i/o timing table 19-2: clkout and i/o timing requirements param no. sym characteristic min typ? max units conditions 10 t os h2 ck losc1 to clkout ?75200ns (note 1) 11 t os h2 ck hosc1 to clkout ?75200ns (note 1) 12 t ck r clkout rise time ? 35 100 ns (note 1) 13 t ck f clkout fall time ? 35 100 ns (note 1) 14 t ck l2 io vclkout to port out valid ? ? 20 ns (note 1) 15 t io v2 ck h port input valid before clkout t osc + 200 ns ? ? ns (note 1) 16 t ck h2 io i port input hold after clkout 0 ? ? ns (note 1) 17 t os h2 io vosc1 (q1 cycle) to port out valid ? 50 150 * ns ??300ns 18 t os h2 io iosc1 (q2 cycle) to port input invalid (i/o in hold time) 100 ? ? ns 19 t io v2 os h port input valid to osc1 (i/o in setup time) 0??ns 20 t io r port output rise time ? 10 40 ns 21 t io f port output fall time ? 10 40 ns 22 t inp int pin high or low time 25 ? ? ns 23 t rbp porta interrupt-on-change high or low time t cy ?? ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 22 23 19 18 15 11 12 16 old value new value
? 2008 microchip technology inc. ds41249e-page 153 pic16f785/hv785 table 19-3: precision internal oscillator parameters figure 19-5: reset, watchdog timer, oscillator start-up timer and power-up timer timing param no. sym characteristic freq. tolerance min typ? max units conditions f10 f osc internal calibrated intosc frequency (1) 1% 7.92 8.00 8.08 mhz v dd = 3.5v, 25 c 2% 7.84 8.00 8.16 mhz 2.5v v dd 5.5v 0 c t a +85 c 5% 7.60 8.00 8.40 mhz 2.0v v dd 5.5v -40 c t a +85 c (ind.) -40 c t a +125 c (ext.) f14 t ioscst oscillator wake-up from sleep start-up time* ? ? 12 24 sv dd = 2.0v, -40 c to +85 c ??714 sv dd = 3.0v, -40 c to +85 c ??611 sv dd = 5.0v, -40 c to +85 c * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: to ensure these oscillator frequency tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1 uf and 0.01 uf values in parallel are recommended. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34
pic16f785/hv785 ds41249e-page 154 ? 2008 microchip technology inc. figure 19-6: brown-out rese t timing and characteristics table 19-4: reset, watchdog timer, oscill ator start-up timer, power-up timer and brown-out reset requirements param no. sym characteristic min typ? max units conditions 30 t mc lmclr pulse width (low) 2 11 ? 18 ? 24 s s v dd = 5.0v, -40c to +85c extended temperature 31 t wdt watchdog timer time-out period (no prescaler) 10 10 17 17 25 30 ms ms v dd = 5.0v, -40c to +85c extended temperature 32 t ost oscillation start-up timer period ? 1024 t osc ??t osc = osc1 period 33* t pwrt power-up timer period 28* 64 132* ms v dd = 5.0v, -40c to +85c 34 t ioz i/o high-impedance from mclr low or watchdog timer reset ??2.0 s 35 v bor brown-out reset voltage 2.025 ? 2.175 v 36 t bor brown-out reset pulse width 100* ? ? sv dd v bor (d005) * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. v bor reset (due to bor) v dd (device in brown-out reset) (device not in brown-out reset) 64 ms time-out (1) 36 note 1: 64 ms delay only if pwrte bit in configuration word is programmed to ? 0 ?.
? 2008 microchip technology inc. ds41249e-page 155 pic16f785/hv785 figure 19-7: timer0 and timer1 external clock timings table 19-5: timer0 and timer1 external clock requirements param no. sym characteristic min typ? max units conditions 40* t t 0h t0cki high pulse width no prescaler 0.5 t cy + 20 ? ? ns with prescaler 10 ? ? ns 41* t t 0l t0cki low pulse width no prescaler 0.5 t cy + 20 ? ? ns with prescaler 10 ? ? ns 42* t t 0p t0cki period greater of: 20 or t cy + 40 n ? ? ns n = prescale value (2, 4, ..., 256) 45* t t 1h t1cki high time synchronous, no prescaler 0.5 t cy + 20 ? ? ns synchronous, with prescaler 15 ? ? ns asynchronous 30 ? ? ns 46* t t 1l t1cki low time synchronous, no prescaler 0.5 t cy + 20 ? ? ns synchronous, with prescaler 15 ? ? ns asynchronous 30 ? ? ns 47* t t 1p t1cki input period synchronous greater of: 30 or t cy + 40 n ? ? ns n = prescale value (1, 2, 4, 8) asynchronous 60 ? ? ns 48 f t 1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) dc ? 200* khz 49 tckez tmr 1 delay from external clock edge to timer increment 2 t osc *?7 t osc *? * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested. t0cki t1cki 40 41 42 45 46 47 49 tmr0 or tmr1
pic16f785/hv785 ds41249e-page 156 ? 2008 microchip technology inc. figure 19-8: capture/comp are/pwm timings (ccp) table 19-6: capture/compare/pwm requirements (ccp) param no. symbol characteristic min typ? max units conditions 50* t cc l ccp1 input low time no prescaler 0.5t cy + 20 ?? ns with prescaler 20 ? ? ns 51* t cc h ccp1 input high time no prescaler 0.5t cy + 20 ?? ns with prescaler 20 ? ? ns 52* t cc p ccp1 input period 3t cy + 40 n ? ? ns n = prescale value (1,4 or 16) 53* t cc r ccp1 output rise time ? 25 50 ns 54* t cc f ccp1 output fall time ? 25 45 ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 19-2 for load conditions. (capture mode) 50 51 52 53 54 ccp1 (compare or pwm mode) ccp1
? 2008 microchip technology inc. ds41249e-page 157 pic16f785/hv785 table 19-7: comparator specifications table 19-8: comparator voltage reference (cv ref ) specifications table 19-9: voltage refere nce (vr) specifications table 19-10: voltage reference output (v ref ) buffer specifications comparator specifications standard operating conditions (unless otherwise stated) operating temperature -40c t a +125c param no. symbol characteristics min typ max units comments c01 v os input offset voltage ? 5 10 mv c02 v cm input common mode voltage 0 ? v dd ? 1.5 v c03 i lc input leakage current ? ? 200* na c04 c mrr common mode rejection ratio +70* ? ? db c05 t rt response time (1) ? ? ? ? 20* 40* ns ns internal output to pin * these parameters are characterized but not tested. note 1: response time measured with one comparator input at (v dd ? 1.5)/2, while the other input transitions from v ss to v dd ? 1.5v. comparator voltage reference specifications standard operating conditions (unless otherwise stated) operating temperature -40c t a +125c param no. symbol characteristics min typ max units comments cv01 cv res resolution ? ? v dd /24* v dd /32 ? ? lsb lsb low range (vrr = 1 ) high range (vrr = 0 ) cv02 absolute accuracy ? ? ? ? 1/4* 1/2* lsb lsb low range (vrr = 1 ) high range (vrr = 0 ) cv03 unit resistor value (r) ? 2k* ? cv04 settling time (1) ?? 10* s * these parameters are characterized but not tested. note 1: settling time measured while vrr = 1 and vr<3:0> transitions from ? 0000 ? to ? 1111 ?. vr voltage reference specifications standard operating conditions (unless otherwise stated) operating temperature -40c t a +125c operating voltage 3.0v v dd 5.5v param no. symbol characteristics min typ max units comments vr01 v rout vr voltage output 1.188 1.176 1.164 1.200 1.200 1.200 1.212 1.224 1.236 v v v t a = 25c 0c t a +85c -40c t a +125c voltage reference output buffer specifications standard operating conditions (unless otherwise stated) operating temperature -40c t a +125c operating voltage 3.0v v dd 5.5v param no. symbol characteristics min typ max units comments vb01* cl external capacitor load ? ? 200 pf * these parameters are characterized but not tested.
pic16f785/hv785 ds41249e-page 158 ? 2008 microchip technology inc. table 19-11: operational amplifie r (opa) module dc specifications table 19-12: operational amplifier (opa) modu le ac specifications table 19-13: two-phase pwm de ad time delay specifications opa dc characteristics standard operating conditions (unless otherwise stated) v cm = 0v, v out = v dd /2, v dd = 5.0v, v ss = 0v, c l = 50pf, r l = 100k operating temperature -40c t a +125c param no. sym characteristics min typ max units comments opa01 v os input offset voltage ? 5?mv opa02* opa03* i b i os input current and impedance input bias current input offset bias current ? ? 2* 1* ? ? na pa opa04* opa05* v cm cmr common mode common mode input range common mode rejection v ss 65 ? 70 v dd ? 1.4 ? v db v dd = 5.0v v cm = v dd /2, freq. = dc opa06a* opa06b* a ol a ol open loop gain dc open loop gain dc open loop gain ? ? 90 60 ? ? db db no load standard load opa07* opa08* vout isc output output voltage swing output short circuit current v ss +100 ? ? 25 v dd ? 100 28 mv ma to v dd /2 (20 k connected to v dd , 20 k + 20 pf to vss) opa10 psr power supply power supply rejection 80 ? ? db * these parameters are characterized but not tested. opa ac characteristics standard operating conditions (unless otherwise stated) v cm = 0v, v out = v dd /2, v dd = 5.0v, v ss = 0v, c l = 50 pf, r l = 100k operating temperature -40c t a +125c param no. symbol characteristics min typ max units comments opa11* gbwp gain bandwidth product ? 3 ? mhz opa12* t on turn on time ? 10 15 s opa13* m phase margin ? 60 ? deg opa14* sr slew rate 2 ? ? v/ s * these parameters are characterized but not tested. dead time delay characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +125c param no. symbol characteristics min typ max units comments pw01* t dly dead time delay 205 231 275 ns f osc = 4 mhz, maximum delay, complementary mode * these parameters are characterized but not tested.
? 2008 microchip technology inc. ds41249e-page 159 pic16f785/hv785 table 19-14: shunt regulator spe cifications (pic16hv785 only) table 19-15: pic16f785/hv78 5 a/d converter characteristics : shunt regulator characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +125c param no. symbol characteristics min typ max units comments sr01 v shunt shunt voltage 4.75 5 5.25 v sr02 i shunt shunt current 4 ? 50 ma sr03* t settle settling time ? ? 150 ns to 1% of final value sr04* c load load capacitance 0.01 ? 10 f bypass capacitor on v dd pin sr05* i snt regulator operating current ? ? 180 a includes band gap reference current * these parameters are characterized but not tested. param no. sym characteristic min typ? max units conditions a01 n r resolution ? ? 10 bits bit a03 e il integral error ? ? 1lsbv ref = 5.0v (external) a04 e dl differential error ? ? 1 lsb no missing codes to 10 bits v ref = 5.0v (external) a06 e off offset error ? ? 1lsbv ref = 5.0v (external) a07 e gn gain error ? ? 1lsbv ref = 5.0v (external) a20 a20a v ref reference voltage 2.2 (4) 1.0 ?? v dd + 0.3 v absolute minimum to ensure 10-bit accuracy a25 v ain analog input voltage v ss ?v ref (5) v a30 z ain recommended impedance of analog voltage source ?? 10k a50 i ref v ref input current* (3) ? ? ? ? 150 1 a ma during v ain acquisition. based on differential of v hold to v ain . transient during a/d conversion cycle. * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: total absolute error includes integral, differential, offset and gain errors. 2: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes. 3: v ref current is from external v ref or v dd pin, whichever is selected as reference input. 4: only limited when v dd is at or below 2.5v. if v dd is above 2.5v, v ref is allowed to go as low as 1.0v. 5: analog input voltages are allowed up to v dd , however the conversion accuracy is limited to v ss to v ref .
pic16f785/hv785 ds41249e-page 160 ? 2008 microchip technology inc. figure 19-9: pic16f785/hv785 a/d conversion timing (normal mode) table 19-16: pic16f785/hv785 a/d conversion requirements param no. sym characteristic min typ? max units conditions 130 t ad a/d clock period 1.6 ? ? st osc -based, v ref 3.0v 3.0* ? ? st osc -based, v ref full range 130 t ad a/d internal rc oscillator period 3.0* 6.0 9.0* s adcs<1:0> = 11 (rc mode) at v dd = 2.5v 2.0* 4.0 6.0* sat v dd = 5.0v 131 t cnv conversion time (not including acquisition time) (1) ?11?t ad set go bit to new data in a/d result register 132 t acq acquisition time (note 2) 5* 11.5 ? ? ? s s the minimum time is the amplifier settling time. this may be used if the ?new? input voltage has not changed by more than 1 lsb (i.e., 4.1 mv @ 4.096v) from the last sampled voltage (as stored on c hold ). 134 t go q4 to a/d clock start ? t osc /2 ? ? if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. these paramete rs are for design guidance only and are not tested. note 1: adresh and adresl registers may be read on the following t cy cycle. 2: see section 12.2 ?a/d acquisition requirements? for minimum conditions. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data 987 3210 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 t cy 6 134 (t osc /2) (1) 1 t cy
? 2008 microchip technology inc. ds41249e-page 161 pic16f785/hv785 figure 19-10: pic16f785/hv785 a/d co nversion timing (sleep mode) table 19-17: pic16f785/hv785 a/d conv ersion requirements (sleep mode) param no. sym characteristic min typ? max units conditions 130 t ad a/d internal rc oscillator period 3.0* 6.0 9.0* s adcs<1:0> = 11 (rc mode) at v dd = 2.5v 2.0* 4.0 6.0* sat v dd = 5.0v 131 t cnv conversion time (not including acquisition time) (1) ?11?t ad 132 t acq acquisition time (note 2) 5* 11.5 ? ? ? s s the minimum time is the amplifier settling time. this may be used if the ?new? input voltage has not changed by more than 1 lsb (i.e., 4.1 mv @ 4.096v) from the last sampled voltage (as stored on c hold ). 134 t go q4 to a/d clock start ?t osc /2 + t cy ? ? if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adres register may be read on the following t cy cycle. 2: see table 12-1 for minimum conditions. 131 130 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data 9 7 3210 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 134 6 8 132 1 t cy (t osc /2 + t cy ) (1) 1 t cy
pic16f785/hv785 ds41249e-page 162 ? 2008 microchip technology inc. notes:
? 2008 microchip technology inc. ds41249e-page 163 pic16f785/hv785 20.0 dc and ac characteristics graphs and tables the graphs and tables provided in this section are for design guidance and are not tested . in some graphs or tables, the data presented are outside specified operating range (i.e., outside specified v dd range). this is for information only and devices are ensured to operate properly only within the specified range. ?typical? represents the mean of the distribution at 25 c. ?maximum? or ?minimum? represents (mean + 3 ) or (mean - 3 ) respectively, where is a standard deviation, over each temperature range. figure 20-1: typical i dd vs. f osc over v dd (ec mode) note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. 3.0v 4.0v 5.0v 5.5v 2.0v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 1 mhz 2 mhz 4 mhz 6 mhz 8 mhz 10 mhz 12 mhz 14 mhz 16 mhz 18 mhz 20 mhz f osc i dd (ma) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c)
pic16f785/hv785 ds41249e-page 164 ? 2008 microchip technology inc. figure 20-2: maximum i dd vs. f osc over v dd (ec mode) figure 20-3: typical i dd vs. f osc over v dd (hs mode) 3.0v 4.0v 5.0v 2.0v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1 mhz 2 mhz 4 mhz 6 mhz 8 mhz 10 mhz 12 mhz 14 mhz 16 mhz 18 mhz 20 mhz f osc i dd (ma) 5.5v typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) hs mode 3.0v 3.5v 4.0v 4.5v 5.0v 5.5v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4 mhz 10 mhz 16 mhz 20 mhz f osc i dd (ma) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c)
? 2008 microchip technology inc. ds41249e-page 165 pic16f785/hv785 figure 20-4: maximum i dd vs. f osc over v dd (hs mode) figure 20-5: typical i dd vs. v dd over f osc (xt mode) hs mode 3.5v 4.0v 4.5v 5.0v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 4 mhz 10 mhz 16 mhz 20 mhz f osc i dd (ma) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) 3.0v 5.5v 0 100 200 300 400 500 600 700 800 900 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i dd ( a) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) 4 mhz 1 mhz
pic16f785/hv785 ds41249e-page 166 ? 2008 microchip technology inc. figure 20-6: maximum i dd vs. v dd over f osc (xt mode) figure 20-7: i dd vs. v dd (lp mode) 0 200 400 600 800 1,000 1,200 1,400 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i dd ( a) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) 4 mhz 1 mhz typical typical 2.0 11 2.5 14.5 3.0 18 3.5 22.25 4.0 26.5 4.5 30.75 5.0 35 5.5 39.25 max maximum 2.0 23 2.5 30.5 30 38 typical maximum 0 10 20 30 40 50 60 70 80 90 2 2.5 3 3.5 4 4.5 5 5.5 v dd (v) i dd (ua) typical: statistical mean @25c maximum: mean (worst case t)+3 typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c)
? 2008 microchip technology inc. ds41249e-page 167 pic16f785/hv785 figure 20-8: typical i dd vs. v dd over f osc (extrc mode) figure 20-9: maximum i dd vs. v dd over f osc (extrc mode) 0 100 200 300 400 500 600 700 800 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i dd ( a) 1 mhz typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) 4 mhz 0 200 400 600 800 1,000 1,200 1,400 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i dd ( a) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) 4 mhz 1 mhz
pic16f785/hv785 ds41249e-page 168 ? 2008 microchip technology inc. figure 20-10: i dd vs. v dd over f osc (lfintosc mode, 31 khz) figure 20-11: typical i dd vs. f osc over v dd (hfintosc mode) lfintosc mode, 31khz typical maximum 0 10 20 30 40 50 60 70 80 v dd (v) i dd ( a) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.0v 3.0v 4.0v 5.0v 5.5v 0 200 400 600 800 1,000 1,200 1,400 1,600 125 khz 250 khz 500 khz 1 mhz 2 mhz 4 mhz 8 mhz f osc i dd ( a) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c)
? 2008 microchip technology inc. ds41249e-page 169 pic16f785/hv785 figure 20-12: maximum i dd vs. f osc over v dd (hfintosc mode) figure 20-13: typical i pd vs. v dd (sleep mode, all peripherals disabled) 2.0v 3.0v 4.0v 5.0v 5.5v 0 200 400 600 800 1,000 1,200 1,400 1,600 1,800 2,000 125 khz 250 khz 500 khz 1 mhz 2 mhz 4 mhz 8 mhz f osc i dd ( a) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) typ 25c max 85c max 125c 2 0.150 1.20 9.00 2.5 0.175 1.285 10.000 3 0.200 1.50 11.00 3.5 0.238 1.483 11.800 4 0.275 1.585 12.600 4.5 0.313 1.688 13.400 5 0.350 1.79 14.20 5.5 0.388 1.893 yp (sleep mode all periphreals disabled) 0.0 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 2.02.53.03.54.04.55.05.5 v dd (v) i pd (ua) typical: statistical mean @25 c
pic16f785/hv785 ds41249e-page 170 ? 2008 microchip technology inc. figure 20-14: maximum i pd vs. v dd (sleep mode, all peripherals disabled) figure 20-15: comparator i pd vs. v dd (both comparators enabled) maximum (sleep mode all periphreals disabled) max 125c max 85c 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd (ua) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) () 0 20 40 60 80 100 120 140 160 180 200 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd (ua) max typical typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c)
? 2008 microchip technology inc. ds41249e-page 171 pic16f785/hv785 figure 20-16: comparator i pd vs. v dd (both comparators enabled) cxsp=1 figure 20-17: bor i pd vs. v dd over temperature typical max 2 362 4 6 0 typical max 0 100 200 300 400 500 600 700 800 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd (ua) typical: statistical mean @25c maximum: mean (worst case temp) + 3 typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) 0 20 40 60 80 100 120 140 160 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( a) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) maximum typical
pic16f785/hv785 ds41249e-page 172 ? 2008 microchip technology inc. figure 20-18: typical wdt i pd vs. v dd over temperature figure 20-19: maximum wdt i pd vs. v dd over temperature typical max 85c max 125c 2 1.700 3.000 4.5 2.5 1.850 3.500 4.75 3 2.000 4.000 5 3.5 2.250 4.750 6.25 4 2.500 5.500 7.5 4.5 2.750 6.250 8.75 5 3.000 7.000 10 5.5 3.250 7.750 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd (ua) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) max. 125c 0.0 2.0 4.0 6.0 8.0 10.0 12.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd (ua) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) max. 85c
? 2008 microchip technology inc. ds41249e-page 173 pic16f785/hv785 figure 20-20: cv ref i pd vs. v dd over temperature (high range) figure 20-21: cv ref i pd vs. v dd over temperature (low range) high range typical max. 85c 0 20 40 60 80 100 120 140 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( a) max. 125c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) typical max. 85c 0 20 40 60 80 100 120 140 160 180 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( a) max. 125c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c)
pic16f785/hv785 ds41249e-page 174 ? 2008 microchip technology inc. figure 20-22: t1osc i pd vs. v dd over temperature (32 khz) figure 20-23: v ol vs. i ol over temperature (v dd = 3.0v) typ 25c max 85c max 125c 2 2.500 7.00 21.00 2.5 2.850 10.50 24.50 3 3.200 14.00 28.00 3.5 3.600 18.50 32.25 4 4.000 23.00 36.50 4.5 4.400 27.50 40.75 5 4.800 32.00 45.00 5.5 5.200 36.50 max 85c max 125c 0.0 10.0 20.0 30.0 40.0 50.0 60.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd (ua) typ 25c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) 6.5 0.2518 0.3336 0.401 0.1503 7 0.2716 0.3609 0.4354 0.1622 7.5 0.2911 0.3884 0.4695 0.1743 8 0.3116 0.4166 0.5049 0.1862 8.5 0.3318 0.4453 0.5413 0.1984 9 0 3524 0 4744 0 5782 0 2107 (vdd = 3v, -40c to 125c) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 i ol (ma) v ol (v) max. 85c max. 125c typical 25c min. -40c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c)
? 2008 microchip technology inc. ds41249e-page 175 pic16f785/hv785 figure 20-24: v ol vs. i ol over temperature (v dd = 5.0v) figure 20-25: v oh vs. i oh over temperature (v dd = 3.0v) 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 i ol (ma) v ol (v) typical: statistical mean @25c maximum: meas + 3 (-40c to 125c) typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) max. 85c typ. 25c min. -40c max. 125c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 i oh (ma) v oh (v) typ. 25c max. -40c min. 125c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c)
pic16f785/hv785 ds41249e-page 176 ? 2008 microchip technology inc. figure 20-26: v oh vs. i oh over temperature (v dd = 5.0v) figure 20-27: ttl input threshold v in vs. v dd over temperature 3.0 3.5 4.0 4.5 5.0 5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 i oh (ma) v oh (v) max. -40c typ. 25c min. 125c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) (ttl input, -40c to 125c) 0.5 0.7 0.9 1.1 1.3 1.5 1.7 2.02.5 3.03.5 4.04.5 5.05.5 v dd (v) v in (v) typ. 25c max. -40c min. 125c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c)
? 2008 microchip technology inc. ds41249e-page 177 pic16f785/hv785 figure 20-28: schmitt trigger input threshold v in vs. v dd over temperature figure 20-29: lfintosc frequency vs. v dd over temperature (31 khz) (st input, -40c to 125c) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) v in (v) v ih max. 125c v ih min. -40c v il min. 125c v il max. -40c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) lfintosc 31khz 0 5,000 10,000 15,000 20,000 25,000 30,000 35,000 40,000 45,000 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) frequency (hz) max. -40c typ. 25c min. 85c min. 125c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c)
pic16f785/hv785 ds41249e-page 178 ? 2008 microchip technology inc. figure 20-30: adc clock period vs. v dd over temperature figure 20-31: typical hfin tosc start-up times vs. v dd over temperature 0 2 4 6 8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) time ( s) 25c 85c 125c -40c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) 0 2 4 6 8 10 12 14 16 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) time ( s) 85c 25c -40c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c)
? 2008 microchip technology inc. ds41249e-page 179 pic16f785/hv785 figure 20-32: maximum hfintosc start-up times vs. v dd over temperature figure 20-33: minimum hfintosc start-up times vs. v dd over temperature -40c to +85c 0 5 10 15 20 25 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) time ( s) -40c 85c 25c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c) -40c to +85c 0 1 2 3 4 5 6 7 8 9 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) time ( s) -40c 25c 85c typical: statistical mean @25c maximum: mean (worst-case temp) + 3 (-40c to 125c)
pic16f785/hv785 ds41249e-page 180 ? 2008 microchip technology inc. figure 20-34: typical hfin tosc frequency change vs. v dd (25c) figure 20-35: typical hfintosc frequency change over device v dd (85c) -5 -4 -3 -2 -1 0 1 2 3 4 5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) change from calibration (%) -5 -4 -3 -2 -1 0 1 2 3 4 5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) change from calibration (%)
? 2008 microchip technology inc. ds41249e-page 181 pic16f785/hv785 figure 20-36: typical hfin tosc frequency change vs. v dd (125c) figure 20-37: typical hfin tosc frequency change vs. v dd (-40c) -5 -4 -3 -2 -1 0 1 2 3 4 5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) change from calibration (%) -5 -4 -3 -2 -1 0 1 2 3 4 5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) change from calibration (%)
pic16f785/hv785 ds41249e-page 182 ? 2008 microchip technology inc. figure 20-38: typical vp6 reference voltage over temperature (3v) figure 20-39: typical vp6 reference voltage over temperature (5v) typical vp6 reference voltage vs. temperature (vdd=3v) 0.52 0.54 0.56 0.58 0.6 0.62 0.64 0.66 -40c 25c 85c 125c temperature (c) vp6 (v) min. max. typical typical vp6 reference voltage vs. temperature (vdd=5v) 0.52 0.54 0.56 0.58 0.6 0.62 0.64 0.66 -40 c 25 c 85 c 125 c temperature (c) vp6 (v) max. typical min.
? 2008 microchip technology inc. ds41249e-page 183 pic16f785/hv785 figure 20-40: typical vp6 reference voltage distribution (5v, 25c) figure 20-41: typical vp6 reference voltage distribution (5v, 85c) 1.1 70 1.176 1 .182 1.188 1.194 1.200 1.206 1.212 1 .218 1.2 24 1.230 voltage (v) number of parts 100 80 60 40 20 0 parts = 150 typical vp6 reference voltage distribution (vdd=3v, 85c) 1.170 1.176 1.182 1.188 1.1 94 1.200 1.206 1.212 1.218 1.224 1.230 voltage (v) number of parts 70 60 50 40 30 20 10 0 parts = 150
pic16f785/hv785 ds41249e-page 184 ? 2008 microchip technology inc. figure 20-42: typical vp6 reference voltage distribution (5v, 125c) figure 20-43: typical vp6 reference voltage distribution (5v, -40c) 1 .170 1.176 1.182 1.188 1.194 1.200 1.206 1.212 1.218 1.224 1.230 voltage (v) number of parts 60 50 40 30 20 10 0 parts = 150 1.170 1.176 1.182 1.188 1.194 1.200 1.206 1.212 1.218 1.224 1.230 voltage (v) number of parts 50 45 40 35 30 25 20 15 10 5 0 parts = 150
? 2008 microchip technology inc. ds41249e-page 185 pic16f785/hv785 figure 20-44: typical vp6 reference voltage distribution (3v, 25c) figure 20-45: typical vp6 reference voltage distribution (3v, 85c) typical vp6 reference voltage distribution (vdd=5v, 25c) 1.170 1.176 1.182 1.188 1.194 1.200 1.206 1.212 1.218 1.224 1.230 voltage (v) number of parts 90 80 70 60 50 40 30 20 10 0 parts = 150 typical vp6 reference voltage distribution (vdd=5v, 85c) 1.170 1.176 1.182 1.188 1.194 1.200 1.206 1.212 1.218 1.224 1.230 voltage (v) number of parts 70 60 50 40 30 20 10 0 parts = 150
pic16f785/hv785 ds41249e-page 186 ? 2008 microchip technology inc. figure 20-46: typical vp6 reference voltage distribution (3v, 125c) figure 20-47: typical vp6 reference voltage distribution (3v, -40c) typical vp6 reference voltage distribution (vdd=5v, 25c) 1.170 1.176 1.182 1.1 88 1.1 94 1.200 1.206 1.2 12 1.2 18 1.224 1.2 30 voltage (v) number of parts 40 35 30 25 20 15 10 5 0 parts = 150 1.170 1.176 1.182 1.188 1.194 1.200 1.20 6 1.212 1.21 8 1.224 1.230 1.236 voltage (v) number of parts 35 30 25 20 15 10 5 0 parts = 150
? 2008 microchip technology inc. ds41249e-page 187 pic16f785/hv785 21.0 packaging information 21.1 package marking information the following sections give the technical details of the packages. 20-lead pdip xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn example pic16f785-i/p 0810017 20-lead soic (.300?) xxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn example pic16f785 -e/so 0810017 20-lead ssop xxxxxxxxxxx xxxxxxxxxxx yywwnnn example pic16f785 -i/ss 0810017 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e * standard pic ? device marking consists of microchip part number, year code, week code, and traceability code. for pic device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. 20-lead qfn example xxxxxxx xxxxxxx ywwnnn 16f785 -i/ml 0810017
pic16f785/hv785 ds41249e-page 188 ? 2008 microchip technology inc.

!"# $% &" ' ()"&'"!&) & #*&& & # +%&,& !& - ' !!#.#&"# '#%!
&"!!#%!
&"!!!& $ #/
!# ' !#&
.0 1,2 1!' ! & $& " !**&"&& ! 3& '!&" &
4 #*!(
! ! &
4
%&& #& &&
255***'
'5
4 6&! 7,8. ' !9'&! 7 7: ; 7"') %! 7 & 1,
& & < < # #4 4 !! - 1! & & < < "# &"# =#& . - - - # #4 =#& . > : 9 & > - ?
& & 9 - 9 #4 !! > 6
9 #=#& ) ? 9* 9 #=#& ) > : *
+ 1 < < - n e1 note 1 d 123 a a1 a2 l e b1 b e c eb
* , 1
? 2008 microchip technology inc. ds41249e-page 189 pic16f785/hv785
! ! "# $%& !' !"# $% &" ' ()"&'"!&) & #*&& & # +%&,& !& - ' !!#.#&"# '#%!
&"!!#%!
&"!!!& $ #''
!# ' !#&
.0 1,2 1!' ! & $& " !**&"&& ! .32 % ' !("!"*&"&& (%%'&
"
! ! 3& '!&" &
4 #*!(
! ! &
4
%&& #& &&
255***'
'5
4 6&! 99.. ' !9'&! 7 7: ; 7"') %! 7 & 1, : 8 & < < ? # #4 4 !! < < &#%%+ < - : =#& . -1, # #4 =#& . 1, : 9 & >1, ,'% @
&a < 3&9 & 9 < 3&
& 9 .3 3& b < >b 9 #4 !! < -- 9 #=#& ) - < #%&
b < b #%& 1&&' b < b d e e1 e b 123 note 1 a a1 a2 h h c l1 l n
* , 1
pic16f785/hv785 ds41249e-page 190 ? 2008 microchip technology inc.
()* ! &% !
!"# $% &" ' ()"&'"!&) & #*&& & # ' !!#.#&"# '#%!
&"!!#%!
&"!!!& $ #''
!# - ' !#&
.0 1,2 1!' ! & $& " !**&"&& ! .32 % ' !("!"*&"&& (%%'&
"
! ! 3& '!&" &
4 #*!(
! ! &
4
%&& #& &&
255***'
'5
4 6&! 99.. ' !9'&! 7 7: ; 7"') %! 7 & ?1, : 8 & < < # #4 4 !! ? > &#%% < < : =#& . > > # #4 =#& . - ? : 9 & ? 3&9 & 9 3&
& 9 .3 9 #4 !! < 3& b b >b 9 #=#& ) < -> l l1 a2 c e b a1 a 12 note 1 e1 e d n
* , 1
? 2008 microchip technology inc. ds41249e-page 191 pic16f785/hv785
+ , #
*- . /0/0%1 +, !"# $% &" ' ()"&'"!&) & #*&& & # 4 !!*!"& # - ' !#&
.0 1,2 1!' ! & $& " !**&"&& ! .32 % ' !("!"*&"&& (%%'&
"
! ! 3& '!&" &
4 #*!(
! ! &
4
%&& #& &&
255***'
'5
4 6&! 99.. ' !9'&! 7 7: ; 7"') %! 7 & 1, : 8 & > &#%% ,&&4 !! - .3 : =#& . 1, .$
! ##=#& . ? > : 9 & 1, .$
! ##9 & ? > ,&&=#& ) > - ,&&9 & 9 - ,&& & .$
! ## c < < d exposed pad e e2 2 1 n top view note 1 n l k b e d2 2 1 a a1 a3 bottom view
* , ?1
pic16f785/hv785 ds41249e-page 192 ? 2008 microchip technology inc. 3& '!&" &
4 #*!(
! ! &
4
%&& #& &&
255***'
'5
4
? 2008 microchip technology inc. ds41249e-page 193 pic16f785/hv785 appendix a: data sheet revision history revision a this is a new data sheet. revision b updates throughout document. revision c revised part number to include ?hv785?; added pwm setup example; added voltage regulator secton. revision d revised vrout min./max. limits in table 19-9. revision e adding characterization data and small updates and reformatting. appendix b: migrating from other pic ? devices this discusses some of the issues in migrating from the pic16f684 pic ? device to the pic16f785/hv785. b.1 pic16f684 to pic16f785/hv785 table b-1: feature comparison feature pic16f684 pic16f785 max operating speed 20 mhz 20 mhz max program memory (words) 2048 2048 sram (bytes) 128 128 a/d resolution 10-bit 10-bit data eeprom (bytes) 256 256 timers (8/16-bit) 2/1 2/1 oscillator modes 8 8 brown-out reset y y internal pull-ups ra0/1/2/4/5 mclr ra0/1/2/3/4/5 mclr interrupt-on-change ra0/1/2/3/4/5 ra0/1/2/3/4/5 comparator 2 ccp eccp y op amps n 2 pwm n two-phase ultra low-power wake-up yn extended wdt y y software control option of wdt/bor yy intosc frequencies 32 khz - 8mhz 32 khz - 8mhz clock switching y y
pic16f785/hv785 ds41249e-page 194 ? 2008 microchip technology inc. notes:
? 2008 microchip technology inc. ds41249e-page 195 pic16f785/hv785 index a a/d ...................................................................................... 79 acquisition requirements ........................................... 86 analog port pins ......................................................... 80 associated registers .................................................. 89 block diagram............................................................. 79 calculating acquisition time....................................... 86 channel selection....................................................... 80 configuration and operation....................................... 80 configuring.................................................................. 85 configuring interrupt ................................................... 85 conversion clock........................................................ 80 effects of reset........................................................... 89 internal sampling switch (rss) impedance ................ 86 operation during sleep .............................................. 88 output format............................................................. 81 reference voltage (v ref )........................................... 80 source impedance...................................................... 86 special event trigger.................................................. 89 specifications............................................ 159, 160, 161 starting a conversion ................................................. 81 using the eccp trigger ............................................. 89 absolute maximum ratings .............................................. 141 ac characteristics load conditions ........................................................ 150 adcon0 register............................................................... 83 adcon1 register............................................................... 84 analog-to-digital converter. see a/d ansel register.................................................... 93, 94, 101 ansel0 register................................................................ 82 ansel1 register................................................................ 82 assembler mpasm assembler................................................... 138 b block diagrams (ccp) capture mode operation ................................. 58 a/d .............................................................................. 79 analog input model ..................................................... 87 ccp pwm................................................................... 60 clock source............................................................... 23 comparator 1 .............................................................. 64 comparator 2 .............................................................. 66 compare ..................................................................... 58 cvref........................................................................... 71 fail-safe clock monitor (fscm) ................................. 31 in-circuit serial programming connections.............. 125 interrupt logic ........................................................... 118 on-chip reset circuit ............................................... 109 opa module................................................................ 75 pic16f785/hv785........................................................ 5 ra0 pin....................................................................... 38 ra1 pin....................................................................... 38 ra2 pin....................................................................... 39 ra3 pin....................................................................... 39 ra4 pin....................................................................... 40 ra5 pin....................................................................... 40 rb4 and rb5 pins ...................................................... 43 rb6 pin....................................................................... 43 rb7 pin....................................................................... 43 rc0 and rc1 pins...................................................... 43 rc0, rc6 and rc7 pins ............................................ 46 rc1 pin....................................................................... 46 rc2 and rc3 pins ..................................................... 47 rc4 pin ...................................................................... 47 rc5 pin ...................................................................... 48 resonator operation .................................................. 25 timer1 ........................................................................ 51 timer2 ........................................................................ 56 tmr0/wdt prescaler ................................................ 49 two phase pwm complementary output mode .......................... 101 simplified diagram ............................................. 92 single phase example ....................................... 98 vr reference ............................................................. 74 watchdog timer (wdt)............................................ 121 brown-out reset (bor).................................................... 110 associated registers................................................ 112 calibration ................................................................ 111 specifications ........................................................... 154 timing and characteristics ....................................... 154 c c compilers mplab c18 .............................................................. 138 mplab c30 .............................................................. 138 capture module. see capture/compare/pwm (ccp) capture/compare/pwm (ccp) .......................................... 57 associated registers.................................................. 62 associated registers w/ capture/compare/timer1 ... 59 capture mode ............................................................. 58 ccp1 pin configuration ............................................. 58 compare mode ........................................................... 58 ccp1 pin configuration ..................................... 59 software interrupt mode ..................................... 59 special event trigger and a/d conversions ...... 59 timer1 mode selection....................................... 59 prescaler .................................................................... 58 pwm mode................................................................. 60 duty cycle .......................................................... 61 effects of reset .................................................. 62 example pwm frequencies and resolutions .... 61 operation in power managed modes ................. 62 operation with fail-safe clock monitor .............. 62 setup for operation ............................................ 62 setup for pwm operation .................................. 62 specifications ........................................................... 156 timer resources ........................................................ 57 ccp. see capture/compare/pwm (ccp) ccp1con register............................................................ 57 ccpr1h register............................................................... 57 ccpr1l register ............................................................... 57 clock sources..................................................................... 23 cm1con0 .......................................................................... 65 cm2con1 .......................................................................... 68 code examples assigning prescaler to timer0.................................... 50 assigning prescaler to wdt....................................... 50 changing between capture prescalers ..................... 58 data eeprom read................................................ 105 data eeprom write ................................................ 105 eeprom write verify .............................................. 105 indirect addressing ..................................................... 22 initializing a/d............................................................. 85 initializing porta ...................................................... 35 initializing portb ...................................................... 42 initializing portc ...................................................... 45
pic16f785/hv785 ds41249e-page 196 ? 2008 microchip technology inc. interrupt context saving ........................................... 120 code protection ................................................................ 124 comparator module ............................................................ 63 associated registers .................................................. 74 c1 output state versus input conditions ................... 63 c2 output state versus input conditions ................... 66 comparator interrupts ................................................. 69 effects of reset........................................................... 69 comparator voltage reference (cv ref ) specifications............................................................ 157 comparators c2out as t1 gate ..................................................... 52 specifications............................................................ 157 compare module. see capture/compare/pwm (ccp) config register.............................................................. 108 configuration bits.............................................................. 107 customer change notification service ............................. 201 customer notification service........................................... 201 customer support ............................................................. 201 d data eeprom memory associated registers ................................................ 106 code protection ................................................ 103, 106 data memory......................................................................... 9 dc and ac characteristics graphs and tables ................................................... 163 dc characteristics extended and industrial ............................................ 148 industrial and extended ............................................ 143 development support ....................................................... 137 device overview ................................................................... 5 e eeadr register ............................................................... 103 eecon1 register ............................................................. 104 eecon2 register ............................................................. 104 eedat register................................................................ 103 eeprom data memory avoiding spurious write............................................ 105 reading..................................................................... 105 write verify ............................................................... 105 writing ....................................................................... 105 effects of reset a/d module ................................................................. 89 comparator module .................................................... 69 opa module................................................................ 77 pwm mode ................................................................. 62 electrical specifications .................................................... 141 errata .................................................................................... 4 f fail-safe clock monitor....................................................... 31 fail-safe condition clearing ....................................... 32 reset and wake-up from sleep .................................. 32 firmware instructions........................................................ 127 fuses. see configuration bits g general purpose register file.............................................. 9 i id locations ...................................................................... 124 in-circuit debugger ........................................................... 125 in-circuit serial programming (icsp) ............................... 124 indirect addressing, indf and fsr registers.................... 22 instruction format............................................................. 127 instruction set................................................................... 127 addlw..................................................................... 129 addwf..................................................................... 129 andlw..................................................................... 129 andwf..................................................................... 129 movf ....................................................................... 132 rrf .......................................................................... 133 sleep ...................................................................... 133 sublw ..................................................................... 134 subwf..................................................................... 134 swapf ..................................................................... 134 tris ......................................................................... 134 xorlw .................................................................... 134 xorwf .................................................................... 135 bcf .......................................................................... 129 bsf........................................................................... 129 btfsc ...................................................................... 130 btfss ...................................................................... 130 call......................................................................... 130 clrf ........................................................................ 130 clrw ....................................................................... 130 clrwdt .................................................................. 130 comf ....................................................................... 131 decf ........................................................................ 131 decfsz ................................................................... 131 goto ....................................................................... 131 incf ......................................................................... 131 incfsz..................................................................... 131 iorlw ...................................................................... 132 iorwf...................................................................... 132 movlw .................................................................... 132 movwf .................................................................... 132 nop .......................................................................... 132 retfie ..................................................................... 133 retlw ..................................................................... 133 return................................................................... 133 rlf ........................................................................... 133 summary table ........................................................ 128 intcon register................................................................ 17 internal oscillator block intosc specifications ................................................... 153 internal sampling switch (rss) impedance........................ 86 internet address ............................................................... 201 interrupts........................................................................... 117 (ccp) compare .......................................................... 58 a/d.............................................................................. 85 associated registers ................................................ 119 comparator................................................................. 69 context saving ......................................................... 120 data eeprom memory write .................................. 104 interrupt-on-change ................................................... 37 oscillator fail (osf) ................................................... 31 porta interrupt-on-change..................................... 118 ra2/int .................................................................... 118 tmr0 ........................................................................ 118 tmr1 .......................................................................... 52 tmr2 to pr2 match ............................................. 55, 56 intosc specifications ..................................................... 153 ioca (interrupt-on-change) ............................................... 37 ioca register..................................................................... 37 l load conditions................................................................ 150
? 2008 microchip technology inc. ds41249e-page 197 pic16f785/hv785 m mclr ................................................................................ 110 internal ...................................................................... 110 .............................................................................................. 9 data .............................................................................. 9 data eeprom memory............................................ 103 program ........................................................................ 9 .......................................... 201, 193, 138, 139, 137, 139, 138 o opa2con register ............................................................ 76 opcode field descriptions ............................................. 127 operational amplifier (opa) module ac specifications.............................................. 158, 159 associated registers .................................................. 77 dc specifications...................................................... 158 option_reg register ...................................................... 17 osccon register.............................................................. 33 oscillator associated registers .................................................. 34 oscillator specifications.................................................... 151 oscillator start-up timer (ost) specifications............................................................ 154 oscillator switching fail-safe clock monitor............................................... 31 two-speed clock start-up.......................................... 30 osctune oscillator tuning register (address 90h) ................... 28 p packaging ......................................................................... 187 pcl and pclath ............................................................... 21 stack ........................................................................... 21 pcon power control register (address 8eh) .................................................................... 20 pcon register ................................................................. 112 picstart plus development programmer ..................... 140 pie1 register...................................................................... 18 pin diagram ...................................................................... 2, 3 pinout descriptions pic16f684.................................................................... 6 pir1 register...................................................................... 19 porta................................................................................ 35 additional pin functions ............................................. 36 interrupt-on-change ............................................ 37 weak pull-up ...................................................... 36 associated registers .................................................. 41 pin descriptions and diagrams................................... 38 ra0 ............................................................................. 38 ra1 ............................................................................. 38 ra2 ............................................................................. 39 ra3 ............................................................................. 39 ra4 ............................................................................. 40 ra5 ............................................................................. 40 specifications............................................................ 152 portb................................................................................ 42 associated registers .................................................. 44 pin descriptions and diagrams................................... 43 rb4 ............................................................................. 43 rb5 ............................................................................. 43 rb6 ............................................................................. 43 rb7 ............................................................................. 43 portc ............................................................................... 45 associated registers ............................................ 34, 48 pin descriptions and diagrams .................................. 46 rc0 ............................................................................ 46 rc1 ............................................................................ 46 rc2 ............................................................................ 47 rc3 ............................................................................ 47 rc4 ............................................................................ 47 rc5 ............................................................................ 48 rc6 ............................................................................ 46 rc7 ............................................................................ 46 specifications ........................................................... 152 power-down mode (sleep)............................................... 123 power-up timer (pwrt) .................................................. 110 specifications ........................................................... 154 power-up timing delays................................................... 112 precision internal oscillator parameters .......................... 153 prescaler shared wdt/timer0................................................... 50 switching prescaler assignment ................................ 50 program memory .................................................................. 9 map and stack.............................................................. 9 programming, device instructions.................................... 127 pwm. see two phase pwm pwmclk register.............................................................. 94 pwmcon0 register........................................................... 93 pwmcon1 register......................................................... 101 pwmph1 register.............................................................. 95 pwmph2 register.............................................................. 96 r reader response............................................................. 202 read-modify-write operations ......................................... 127 refcon (vr control)........................................................ 73 register intcon interrupt control register (ad- dress 0bh, 8bh, 10bh or 183h) .................................... 17 ioca (interrupt-on-change) ....................................... 37 wpua (weak pull-up porta)................................... 36 registers adcon0 (a/d control 0)............................................ 83 adcon1 (a/d control 1)............................................ 84 ansel (analog select) ................................ 93, 94, 101 ansel0 (analog select 0) ......................................... 82 ansel1 (analog select 1) ......................................... 82 ccp1con (ccp operation) ...................................... 57 ccpr1h..................................................................... 57 ccpr1l ..................................................................... 57 cm1con0 (c1 control) ............................................. 65 cm1con0 (c2 control) cm2con0 .......................................................... 67 cm2con1 (c2 control) ............................................. 68 config (configuration word) ................................. 108 data memory map ...................................................... 10 eeadr (eeprom address) .................................... 103 eecon1 (eeprom control 1) ................................ 104 eecon2 (eeprom control 2) ................................ 104 eedat (eeprom data) .......................................... 103 intcon (interrupt control) ........................................ 17 ioca (interrupt-on-change porta).......................... 37 op amp 2 control register (opa2con) ................... 76 option_reg option register .......................................... 16 option_reg (option) .............................................. 17 osccon (oscillator control)..................................... 33 pcon (power control) ............................................. 112 pie1 (peripheral interrupt enable 1) .......................... 18
pic16f785/hv785 ds41249e-page 198 ? 2008 microchip technology inc. pir1 (peripheral interrupt register 1) ........................ 19 porta........................................................................ 35 portb........................................................................ 42 portc ....................................................................... 45 pwmclk (pwm clock control) ................................. 94 pwmcon0 (pwm control 0) ..................................... 93 pwmcon1 (pwm control 1) ................................... 101 pwmph1 (pwm phase 1 control) .............................. 95 pwmph2 (pwm phase 2 control) .............................. 96 refcon (vr control)................................................ 73 reset values............................................................. 114 reset values (special registers) ............................. 116 special function registers ........................................... 9 special register summary ............................. 12, 13, 14 status ...................................................................... 15 status .................................................................. 16, 109 t1con (timer1 control)............................................. 53 t2con (timer2 control)............................................. 55 trisa (tri-state porta) ........................................... 36 trisb (tri-state portb) ........................................... 42 trisc (tri-state portc) ........................................... 45 wdtcon (watchdog timer control)........................ 122 wpua (weak pull-up porta) ................................... 36 resets ............................................................................... 109 power-on reset ....................................................... 110 revision history ................................................................ 193 rrf instruction ................................................................. 133 s sleep instruction ................................................................. 133 power-down mode ................................................... 123 wake-up ................................................................... 123 wake-up using interrupts......................................... 123 software simulator (mplab sim)..................................... 138 special event trigger.......................................................... 89 special function registers ................................................... 9 specifications .................................................................... 158 status register................................................................ 15 status register............................................................ 16, 109 sublw instruction............................................................ 134 subwf instruction............................................................ 134 swapf instruction............................................................ 134 t time-out sequence........................................................... 112 timer0 ................................................................................. 49 associated registers .................................................. 50 external clock............................................................. 50 interrupt....................................................................... 49 operation .................................................................... 49 prescaler..................................................................... 50 specifications............................................................ 155 timer1 ................................................................................. 51 associated registers .................................................. 54 asynchronous counter mode ..................................... 54 reading and writing ........................................... 54 interrupt....................................................................... 52 modes of operations................................................... 52 operation during sleep .............................................. 54 oscillator ..................................................................... 54 prescaler..................................................................... 52 specifications............................................................ 155 timer1 gate inverting gate ..................................................... 52 selecting source ................................................ 52 tmr1h register ......................................................... 51 tmr1l register.......................................................... 51 timer2................................................................................. 55 associated registers .................................................. 56 operation .................................................................... 55 postscaler................................................................... 55 pr2 register .............................................................. 55 prescaler .................................................................... 55 tmr2 register............................................................ 55 tmr2 to pr2 match interrupt............................... 55, 56 timing diagrams a/d conversion......................................................... 160 a/d conversion (sleep mode) .................................. 161 brown-out reset (bor)............................................ 154 brown-out reset situations ...................................... 111 capture/compare/pwm (ccp) ................................ 156 clkout and i/o ...................................................... 152 external clock........................................................... 151 fail-safe clock monitor (fscm)................................. 32 int pin interrupt ....................................................... 119 reset, wdt, ost and power-up timer ................... 153 time-out sequence case 1 .............................................................. 113 case 2 .............................................................. 113 case 3 .............................................................. 113 timer0 and timer1 external clock ........................... 155 timer1 incrementing edge ......................................... 52 two phase pwm complementary output .................................... 102 start-up............................................................... 97 two speed start-up.................................................... 31 two-phase pwm auto-shutdown ................................................... 97 wake-up from interrupt............................................. 124 timing parameter symbology .......................................... 150 tris instruction ................................................................ 134 trisa register................................................................... 36 trisb register................................................................... 42 trisc register................................................................... 45 two phase pwm ................................................................ 91 activating .................................................................... 91 active output level .................................................... 92 associated registers ................................................ 102 auto-shutdown............................................................ 92 clock control (pwmclk) ........................................... 94 control register 0 (pwmcon0)................................. 93 control register 1 (pwmcon1)............................... 101 master/slave operation .............................................. 91 output blanking .......................................................... 91 phase 1 control (pwmph1)....................................... 95 phase 2 control (pwmph1)....................................... 96 pwm duty cycle......................................................... 91 pwm frequency ......................................................... 91 pwm period................................................................ 91 pwm phase................................................................ 91 pwm phase resolution.............................................. 91 shutdown.................................................................... 92 two-phase pwm dead time delay ...................................................... 158 two-speed clock start-up mode........................................ 30
? 2008 microchip technology inc. ds41249e-page 199 pic16f785/hv785 v voltage reference (vr) specifications............................................................ 157 voltage reference output (v ref ) b uffer specifications............................................................ 157 voltage references ............................................................ 70 associated registers .................................................. 74 configuring cvref ....................................................... 70 cvref (comparator reference)................................... 70 cvref accuracy ........................................................... 70 fixed vr reference ..................................................... 73 vr stabilization........................................................... 74 v ref . s ee a/d reference voltage w wake-up using interrupts ................................................. 123 watchdog timer (wdt) .................................................... 121 associated registers ................................................ 122 clock source............................................................. 121 modes ....................................................................... 121 period........................................................................ 121 specifications............................................................ 154 wdtcon register ........................................................... 122 wpua (weak pull-up porta) ........................................... 36 wpua register................................................................... 36 www address.................................................................. 201 www, on-line support ....................................................... 4 x xorlw instruction ........................................................... 134 xorwf instruction ........................................................... 135
pic16f785/hv785 ds41249e-page 200 ? 2008 microchip technology inc. notes:
? 2008 microchip technology inc. ds41249e-page 201 pic16f785/hv785 the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com
pic16f785/hv785 ds41249e-page 202 ? 2008 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds41249e pic16f785/hv785 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2008 microchip technology inc. ds41249e-page 203 pic16f785/hv785 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device: pic16f785 (1) , pic16hv785 (1) , pic16f785t (2) , pic16hv785t (2) ; v dd range 4.2v to 5.5v pic16f785 (1) , pic16hv785 (1) , pic16f785t (2) , pic16hv785t (2) ; v dd range 2.0v to 5.5v temperature range: i= -40 c to +85 c industrial) e= -40 c to +125 c extended) package: ml = qfn p=pdip so = soic ss = ssop pattern: qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic16f785 - e/so 301 = extended temp., soic package. b) pic16f785 - i/ml = industrial temp., qfn package. note 1: f = standard voltage range lf = wide voltage range 2: t = in tape and reel plcc, and tqfp packages only.
ds41249e-page 204 ? 2008 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 w orldwide s ales and s ervice 01/02/08

▲Up To Search▲

Price & Availability of PIC16HV785T-EML

	To Download PIC16HV785T-EML Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .